Changing The Meaning Of Sign-Off

Chip development teams are faced with an ever-increasing number of power integrity and reliability challenges these days, especially as designs adopt FinFET technology. Even those with the most thorough sign-off checks often encounter unexpected surprises that quickly turn into tape-out hurdles, or worse yet, extensive re-design. The best way to avoid this scenario and ensure a smoother sign-off process prior to tape-out involves making a clear distinction between using a Sign-Off tool for a design vs. Signing Off a design at the end. This blog will discuss the differences between the two approaches and how a sign-off tool used throughout the design flow addresses these challenges.

Let’s start by going back to the “Good ‘Ole Days” of chip design. Designers once spoke of design “sign-off” in a way that might evoke images of an artist putting the final touches on a masterpiece before hitting the gallery. Reassured that it had been properly checked for reliability and power integrity, the signed-off masterpiece would soon find its way to being fabricated, followed by testing in the lab. There, it would be revealed that the final edits done during ”sign-off” miraculously saved it from any annoying electromigration (EM) or IR drop issues that would have otherwise gotten in the way of a perfectly functional design. Also, as long as electro-static discharge (ESD) structures followed basic rules and standard footprints and placement, everything would turn out okay. Adding a bit of margin to the design, this “correct by construction” approach seemed to work well.

Then, process engineers started waving more goodies in front of designers, claiming performance gains that sounded like familiar lines from the past – “faster, smaller, lower voltage.” What they didn’t explicitly mention are the design and reliability challenges presented by these new process technologies. Aside from new basic layout challenges due to more stringent rules, new design innovations using the latest devices also required a careful consideration of other effects such as noise coupling through the substrate, signals, or power rails.

The once idealistic picture of “single sign-off and you’re done” is now a fairy tale for modern designs using the latest deep sub-micron process technologies (28nm and below) and FinFET devices. Far from being an afterthought or a final “stage” of a chip design (and by extension, the system design), reliability and power integrity have ascended the ranks on checklists of forward thinking design teams. In addition, they are now tightly interwoven with design itself, thus graduating from highly ranked checklist items to actually being cemented into the design process itself.

Consider sign-off checks throughout the design process
With designs incorporating an increased number of voltage domains, clocks, activity profiles, and power management schemes in denser layouts, it becomes hard to correlate changes in architectural decisions to power integrity and reliability issues without properly assessing the effects at various stages of the design. In addition to avoiding pitfalls, a staged approach also reveals potential cost-cutting opportunities along the way, as customizing the power grid or the number of components such as power gates, high-VT cells, or decaps to meet specifications that can prevent over-design.

Design teams are finding ways to reduce power before any physical implementation even takes place by doing power estimation and optimization at the architectural phase, using the RTL design. Using these power estimates to perform “early analysis” of the chip or blocks that comprise the chip, designers can start projecting the eventual power integrity and reliability concerns on their physical design. Identifying gross violations and power planning mishaps early on saves headaches later. As progress is made on different aspects of the design, such as finalizing specific power grid topologies and power gate sizes/placements, deciding on a package design, and determining activity factors/vectors of various blocks, the design is re-evaluated at every step for transient power noise effects, EM and ESD robustness.

By leveraging the accuracy and versatility of sign-off tools from early physical design planning to eventual sign-off, design teams are able to:

1. See the direct impact that various incremental design decisions play on the ultimate chip performance;
2. Correct for undesired effects seen as each significant change is introduced, and
3. Save from excessive over- or under-design that may have greater business implications down the road.

A very good example of benefits derived from incremental analysis is the recent trend of co-designing the chip with the package, where effects on the die and the package are simultaneously analyzed to see where bottlenecks lie as both designs evolve. Subsequent design decisions are then made on how either or both can be altered to provide optimal performance. The “one size fits all” package is also becoming a thing of the past, with greater customization taking place on both the die and the package to account for detrimental L(di/dt) or RC parasitic effects. With the latest tool advancements, die designers can observe IR effects on the imported package layout itself and provide valuable feedback to the package team for potential areas of improvement.

These types of a paradigm shifts in analysis techniques to meet new demands is nothing new. Recall a time when designing a digital section with an analog front end in mind was foreign to digital designers. Similarly, when accounting for dynamic IR through transient simulations was foreign to chip designers, who found that simply adding more margin to their static IR results was sufficient for sign off. You see where this is going – we cannot ignore new physics that creep up on us just because we were not used to these effects in the not too distant past.

Anyone taking the bold next step into FinFET or tri-gate technologies will be greeted by new challenges associated with increased thermal effects. In addition, EM limits are up to 30% more stringent, making standalone EM analysis on sub-blocks (standard cells and IPs) using sign-off tools prior to a full-chip analysis even more critical so that problems can be better isolated and resolved. Though patchwork such as simple metal width adjustments may have worked in the past for small EM violations, teams now face the prospect of non-trivial architectural or physical re-design due to unforeseen effects such as large inrush current caused by bad switch placement or sensitive timing paths impacted by dynamic voltage drop.

To avoid costly and time-consuming iterations of parts (or the entirety) of the design due to significant issues confronted at the final sign-off stage, it is wise to make a clear distinction between using a Sign-Off tool for a design vs. Signing Off a design. Using a Sign-Off tool means that you depend upon such a tool at various stages of the design cycle to provide the accuracy needed to efficiently drive your design to completion and achieve post-silicon success. It doesn’t mean that all your problems are solved by running the tool once at the end of a design cycle to sign off. In fact, designers are often shell-shocked by results when they wait until the end to analyze the effects of power noise and reliability.

As they say, better safe than sorry – to ease the burden of your final sign-off concerns, think about how to properly account for power integrity and reliability effects as the design evolves from start to finish.

To learn about ANSYS RedHawk, watch this 2-minute video on how RedHawk, the full-chip power integrity sign-off platform, is ready for 16nm FinFET based designs.