On-premises compute capacity has become a bottleneck for circuit simulation.
By Nebabie Kebebew and Nigel Bleasdale
Driven by the explosion of big data and expanding applications, chip design complexity is increasing. Applications such as high-performance computing (HPC), the Internet of Things (IoT), automotive, and 5G mobile and communications coupled with advanced process technology nodes require running a large number of circuit simulations to ensure the circuits function correctly. This means even more simulation runtime and the requirement for more compute resources. On-premises compute capacity has undeniably become a bottleneck. Cloud computing is a viable solution to drastically reduce simulation runtime for circuit simulation workflows. In collaboration with Amazon Web Services (AWS), Siemens EDA has made a cloud-ready Analog FastSPICE (AFS) platform available to accelerate design innovation.
The increasing complexity of chip designs requires designers to run extensive circuit simulations in many levels of the design hierarchies to ensure robust designs that meet power, performance, and area (PPA) requirements and ultimately achieve high silicon yield.
Circuit simulation is inherently a compute-intensive workflow, with long runtimes of days to weeks. Cloud computing has dramatically reduced circuit simulation runtimes, providing design teams with scalable, on-demand, cost-effective computing resources. By leveraging on-demand high-performance computing, design teams can offload peak compute capacity needs and run high-priority simulations during the design development cycle. As a result, design teams can complete simulation jobs that require days to weeks of runtime to run in hours.
The cloud-ready AFS platform provides design teams with a scalable, secure and cost-effective circuit simulation workflow. As a result, designers can leverage cloud computing resources to reduce compute resource bottlenecks, improve design robustness, and achieve production schedule predictability.
Today’s circuit design analysis and simulation workflows have several dimensions that lead to vast amounts of simulation, making it one of the most critical bottlenecks in the design IP development cycle. For one, these simulation jobs are highly iterative and span the entire IP design and verification cycle, including design scoping, development and debugging (figure 1).
Fig. 1: IP design and verification workflow.
Furthermore, designs with advanced process nodes mean significantly more simulation jobs to account for all design variations due to increasing parasitics, increasing variability, device noise, and the requirement for reliability analysis (figure 2). Every new process node migration results in about 3X more simulations than the previous node, and this includes verification of increased IP content per chip in the latest technology node.
Also, a typical design IP sub-block can take weeks to cover its simulation plan – the design needs to be iterated across various process design kits (PDKs) and post-layout revisions to ensure the desired functionality. These simulation jobs are computationally intensive, leading to long simulation runtimes of days to weeks.
Fig. 2: Increasing design complexity from node-to-node migration.
Semiconductor companies have limited on-premises compute clusters ranging from hundreds to thousands of CPUs. These compute clusters are typically shared across the company for concurrent design projects and various types of other EDA workflows. The availability of computing resources limits the ability of each designer to run simulations during the entire design cycle. Companies’ current on-premises compute clusters (data centers) are left idle in the early design stages and are in very high demand during the chip verification stage, up to the chip tape-out milestone. In addition, to meet the changing computing demand, companies need to continuously invest in new machines and storage systems while maintaining existing systems, all of which can be costly. These challenges in sharing computing resources across designers and varying compute requirements impose a productivity bottleneck and limit the extent to which pre-silicon design and verification space exploration can be conducted, contributing to long design turnaround times, suboptimal designs, and even chip failures.
Circuit simulation workflow is typically a methodology (figure 3) where the designer creates a circuit model in an analog design environment and analyzes it, using a simulator to predict, measure, and verify the behavior and performance of the circuit. This is done against a set of functional, test, and reliability specifications. Over the years, parallel circuit simulation software has advanced to harness the power of parallel computing for compute-intensive analyses and simulations, such as post-layout, Monte Carlo, and PVT simulation – making circuit simulation suitable for massive parallelization.
Fig. 3: Circuit simulation workflow.
Siemens EDA’s Analog FastSPICE platform (AFS) is a simulation technology that provides nm-accurate circuit simulation, mixed-signal simulation, and full-spectrum and multi-tone device noise analysis for verifying analog, RF, mixed-signal, and custom digital circuits. AFS is foundry-certified by the world’s leading foundries delivering SPICE accuracy. AFS is a single executable platform with performance, capacity and functionality. It supports industry-standard netlist syntax and seamlessly integrates into industry-leading EDA design environments. The RF engine in AFS supports Shooting Newton and Harmonic Balance methods with recent innovations. For silicon-accurate characterization, the AFS platform includes comprehensive full-spectrum device noise analysis and integrates with Solido Variation Designer to deliver full variation-aware design coverage in orders-of-magnitude fewer simulations but with the accuracy of brute force techniques.
The AFS eXTreme (AFS XT) platform further enhances performance drastically for large post-layout netlists compared to standard AFS. AFS XT can handle over 300 million elements transient capacity and delivers fast mixed-signal simulation with the Symphony Mixed-Signal platform. Designers use the AFS platform for their toughest circuit verification challenges, including high-speed I/Os, PLLs, ADCs/DACs, CMOS image sensors, wired and wireless transceivers, and embedded memory.
Fig. 4: Analog FastSPICE platform.
In collaboration with AWS, Siemens EDA has made available an optimized, scalable, and validated cloud-ready AFS platform for circuit simulation workflow. AFS platform software running in AWS’ cloud environment and using elastic compute resources enables design teams to accelerate production simulation runtime, reduce compute resource bottlenecks, and improve schedule predictability.
Circuit design teams can use cloudy-ready AFS with AWS cloud to significantly reduce production simulation runtimes by scaling across a diverse set of high-performance computing resources suited for compute-intensive circuit analyses and simulation tasks. Designers no longer must wait for computing machines to be available to run their simulation jobs. Instead, they can complete simulation jobs in a timely fashion and be able to run more simulation iterations and start new simulation jobs in parallel. This gives them the ability to perform exhaustive simulations and efficiently execute the simulation plans and ultimately produce robust designs to meet PPA requirements.
Planning and predicting the quantity and type of on-premises compute resources required for design teams has been challenging for semiconductor companies. As a result, designers often compete for on-premises computing resources during the peak simulation period and at the design tape-out stage, leading to potential delays in production schedules. Access to a virtually unlimited number of diverse sets of compute servers and storage with different performance and memory characteristics provides design teams with options and the flexibility to run circuit simulations quickly.
The scalability of the AFS platform is demonstrated by carrying out several circuit simulation workflows on AWS cloud reference architecture designed and built for optimal performance and scalability (figure 5).
Fig. 5: AWS cloud reference architecture for circuit simulation workflow with AFS.
Working with AWS enables design teams to use the AFS platform and fully leverage AWS’ cloud environment, resources, and high-performance computing services to meet their time-to-market schedules. Some of the key AWS components and services for an optimized and cost-effective circuit simulation workflow with AFS are AWS ParallelCluster with SLURM, Amazon FSx for Lustre, S3, and NICE DCV.
AWS ParallelCluster, an open-source cluster orchestration tool, enables AFS platform users to quickly deploy and manage the compute clusters on AWS. With AWS ParallelCluster, users can have a simple configuration file to model file to model, provision and dynamically scale the HPC resources needed for AFS in an automated and secure manner. The user initiates the creation of a cluster through the AWS ParallelCluster CLI and specification in the configuration file. AWS CloudFormation builds the cluster architecture described in the cluster template file, where the user contributes a few custom settings. Users can quickly terminate the HPC cluster resources after completing the circuit simulation jobs, thus saving usage costs for idle resources.
Amazon FSx for Lustre is a fully-managed high-performance parallel file system that provides cost-effective, scalable, shared storage access for a circuit simulation workflow. FSx for Lustre provides sub-millisecond latencies, up to hundreds of GBs/s of throughput, and millions of IOPS, making it ideal for AFS simulations. NICE DCV is a high-performance remote display protocol that allows secure access to the graphical design environment enabling designers to graphically set up, run and analyze the simulation results. Amazon Simple Storage Service (S3) buckets store simulation input and output data.
Siemens EDA and AWS identified and validated Amazon Elastic Compute Cloud (EC2) virtual machines (figure 6) to enable an optimized and cost-effective circuit simulation workflow. The validation includes profiling diverse and heterogeneous sets of EC2 instances for various circuit simulation use cases and workflows. Using a diversified EC2 instance type strategy provides higher resource flexibility and access, delivering a cost-effective and high-performing cloud architecture suited for circuit simulation workflows.
Fig. 6: Benchmarked and validated Amazon EC2 instance types for circuit simulation workflow with Analog FastSPICE platform.
Siemens EDA works closely with AWS to identify and maintain security protocols and ensure IP is transported, stored and used securely. This includes how data is transferred between the cloud and on-premises machines, how user access points are secured, and how data access is allocated for authorized users within the AWS cloud network.
A secure connection is used for a circuit simulation workflow to transfer data between the cloud and the on-premises machines. The compute nodes of the HPC cluster used for running the workflow are placed in a private subnet (figure 5), ensuring secure access to and from the proprietary design data, software and licenses.
In addition to protecting IP data in transit and at rest, a large part of ensuring cloud security is implementing a robust user identification process, installing traceability measures for actions taken on the cloud, and automating security practices in concert with the company’s protocol. For example, AWS ParallelCluster uses AWS Identity and Access Management (IAM) roles to control permissions associated with the AWS resources deployed to the AWS account. Siemens EDA and AWS work together to identify and advise mutual customers on security requirements and best practices applicable at the user level and all layers of cloud deployment.
Validated results with a Monte Carlo simulation use case demonstrate that a cloud-ready AFS platform achieves effective scalability – up to 8,000 CPUs on AWS. This simulation use case is for a DC-DC converter circuit that required statistical transient analysis. The performance result is displayed for core scaling (figure 7). This showcases that a circuit simulation job that takes days or weeks can be reduced to a few hours of simulation.
Fig. 7: Validated circuit simulation runtime across numbers of CPUs.
The AWS cloud environment configuration settings used to achieve these validated results are captured in AWS CloudFormation templates – key to accelerating the deployment of an optimal AWS reference architecture, enabling designers to adopt a cloud-ready AFS for circuit simulation workflow efficiently.
Designers can interactively measure and view graphical results and analyze them efficiently in the cloud (figure 8).
Fig. 8: Solido Variation Designer, simulation measurement results, viewing through NICE DCV.
Analog FastSPICE platform running on AWS cloud enables the design team to reduce compute resource bottlenecks, significantly accelerate design production schedules, and improve the robustness of the design, enabling design teams to meet PPA requirements and achieve higher silicon yield.
Cloud-ready Analog FastSPICE provides a highly scalable, secure, and cost-effective circuit simulation workflow, enabled by AWS cloud services such as Amazon EC2, Amazon FSx for Lustre, Amazon S3, and AWS CloudFormation. Designers can quickly submit and execute simulation jobs and complete simulation plans efficiently.
Circuit simulation use cases and workflows have been validated on an optimal AWS cloud reference architecture, with effective scaling of up to 8,000 CPUs. AWS CloudFormation enables design project teams to deploy circuit simulation workflows on the cloud quickly and accelerate the completion of circuit simulation to mere hours instead of days or weeks of runtime.
The authors would like to thank Ramy Siha and John Spencer from Siemens EDA for their help and support in setting up the AWS cloud environment. Thank you to Pradeep Thiagarajan, from Siemens EDA, for his advice and contribution to this paper.
This work would not have been possible without the guidance and technical consultation from Dnyanesh Digraskar and Kenneth Chang from Amazon Web Services.
Nigel Bleasdale is a senior principal product engineer for AMS Verification at Siemens EDA.
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