CMOS-Embedded STT-MRAM Arrays In 2xnm Nodes For GP-MCU Applications

A look at robust STT-MRAM technology, including full array functionality with low bit-error rate.


Perpendicular Spin-Transfer Torque (STT) MRAM is a promising technology in terms of read/write speed, low power consumption and non-volatility, but there has not been a demonstration of high density manufacturability at small geometries. In this paper we present an unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS- embedded 40 Mb array. Key features are full array functionality with low BER (bit error rate), process uniformity and reliability, 10 years data retention at 125C with extended endurance to ~ 107 cycles. All achieved with standard BEOL process temperatures. Data retention post 260°C solder reflow temperature cycle is demonstrated.

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