Collaboration Accelerates Moore’s Law

Moore’s Law dictates that the number of transistors in dense, integrated circuits will double approximately every two years. Maintaining this pace of scaling, however, has become increasingly difficult given the ever-increasing complexity inherent with new chip starts.

Additionally, the cost of using leading-edge process technology is prohibitively expensive. As a result, collaboration among industry partners has become absolutely critical to reduce costs and to demonstrate, validate, and scale technology to facilitate rapid market adoption.

Because very few companies have the resources to develop all necessary SoC technology in-house, many are working collaboratively to develop and integrate critical IP blocks into their designs. Given ever-increasing performance requirements and the diversity of IP blocks, having access to the most advanced technology is critical to ensure a successful SoC strategy.

With advanced memory rates at 3200 Mbps and interface rates at 28Gbps and above, partnering is an easy and efficient way to access these technologies. Similarly, demand for end-to-end security solutions embedded in the SoC is growing rapidly in industries such as banking, printing and DRM. The Rambus Partner Program offers preferred access to advanced memory, interfaces, and security technology. The program also bundles core competencies in high-speed interface and security solutions with design and validation tools to support ASIC designers, foundries, IP developers, and EDA companies.

We have accelerated collaboration with a several industry heavyweights on both low power and high performance designs and will present silicon demos at the upcoming ARM TechCon (Oct. 1-3 in Santa Clara, CA) of low-power memory PHYs targeting industry standards, “beyond DDR4” interfaces, and multi-protocol high-speed serial links.

Rambus and Northwest Logic also recently validated interoperability of the R+ DDR4/3 PHY with Northwest Logic’s DDR4/3 SDRAM Controller Core, providing customers with an easy way to integrate a tested and validated PHY/controller combination.

Mutually beneficial partnerships are an absolute must to address the growing need for third party IP in chip designs and the increasingly challenging price, performance, and area requirements associated with today’s complex SoCs.

Combining design services, complementary IP blocks, design and verification tools, and semiconductor manufacturing in a coordinated and efficient manner helps simplify and accelerate design cycles, while simultaneously decreasing costs and creating robust, industry-leading solutions.