A technical paper titled “Plan your defense: A comparative analysis of leakage detection methods on RISC-V cores” was published by researchers at Radboud University.
“Hardening microprocessors against side-channel attacks is a critical aspect of ensuring their security. A key step in this process is identifying and mitigating “leaky” hardware modules, which inadvertently leak information during the execution of cryptographic algorithms. In this paper, we explore how different leakage detection methods, the Side-channel Vulnerability Factor (SVF) and the Test Vector Leakage Assessment (TVLA), contribute to hardening of microprocessors. We conduct experiments on two RISC-V cores, SHAKTI and Ibex, using two cryptographic algorithms, SHA-3 and AES. Our findings suggest that SVF and TVLA can provide valuable insights into identifying leaky modules. However, the effectiveness of these methods can vary depending on the specific core and cryptographic algorithm in use. We conclude that the choice of leakage detection method should be based not only on computational cost but also on the specific requirements of the system and the nature of the potential threats. Our research contributes to developing more secure microprocessors that are robust against side-channel attacks.”
Find the technical paper here. Published March 2024 (preprint).
Miteloudi, Konstantina, Asmita Adhikary, Niels van Drueten, Lejla Batina, and Ileana Buhan. “Plan your defense: A comparative analysis of leakage detection methods on RISC-V cores.” Cryptology ePrint Archive (2024).
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