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Context-Aware SPICE Simulation Improves The Fidelity Of ESD Analysis

Combining static and dynamic approaches to electrostatic discharge verification.

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Electrostatic discharge (ESD) is a major reliability concern for integrated circuit (IC) designs. ESD verification is proving to be a significant challenge at advanced nodes, due to growing IC design complexity and transistor counts. Traditional ESD verification approaches using parasitic extraction followed by SPICE simulation are deficient in providing simulation results in a practical runtime at the large block or full-chip level. Utilizing a revolutionary technique that merges the powerful capabilities of static and dynamic checking using Calibre PERC and Analog FastSPICE (AFS) technologies, the context-aware SPICE flow enables designers to overcome this deficiency while ensuring the fidelity of ESD analysis.

ESD verification

ESD events occur when there is a sudden transfer of static charge between two bodies at different potentials. In the case of ICs, the ESD event occurs when an external charged object touches the IC or a charged IC touches a grounded surface. These events are characterized by a current pulse with a short duration (0.1ns to 100ns) and high current peak magnitude (0.1A to 30A). Two industry standards are widely used to model these events: the human body model (HBM) and the charged device model (CDM) [1]. Figure 1 shows the typical discharge waveforms associated with each standard.


Fig. 1: Typical HBM and CDM discharge waveforms.

Metal–oxide–semiconductor (MOS) devices inside ICs can degrade or suffer irreversible damage due to ESD events. These events can also cause damage to interconnects by exceeding their current density (CD) limits, which can increase interconnect resistance or cause the interconnect to melt, creating opens or shorts.

Various protection structures are used inside ICs to shunt the high ESD current away from the functional or core circuits, preventing damage to the devices. For these protection structures to be effective, they must provide a low resistance path through which current can flow, bypassing the functional blocks and protecting them from damage. ESD verification ensures that these structures are correctly constructed and placed.

ESD verification challenges

To test the robustness of intellectual property (IP) ESD protection structures, designers typically run SPICE simulations on the IP blocks included in their IC design. When running simulations at the IP level, designers often fail to accurately capture back-end-of-line (BEOL) parasitics because global or top-level routing isn’t included in the IP-level block, meaning the parasitics from the routing on higher metals isn’t considered. One way designers work around this limitation is by manually constructing the power/ground (PG) networks so they can approximate or manually calculate these parasitics. Manual processes are inherently error-prone, and there is always the risk of accidentally excluding necessary IP from the schematic.

Some ESD protection schemes use elements that exhibit snapback behavior (figure 2), which is when the voltage “snaps back” (reduces) as the current increases in a region between Vt1 and VH, meaning this area is a negative resistance region. Because of that negative resistance, traditional SPICE simulators can encounter problems converging when simulating these snapback elements, which makes dynamic simulation-based methodology problematic on these circuits.


Fig. 2: Characteristic I-V curve for a snapback ESD element.

An alternative approach is to run a static resistance checker on the design. Resistance values obtained by running a static check engine are compared with the limits set by the foundry. If the path resistance obtained from the static checking engine is within the foundry limit or specification, then the design or IP is considered to pass the ESD check. In most scenarios, running static checking for ESD sign-off is highly recommended and a proven solution. A static checking engine provides greatly improved capacity and runtimes compared to a SPICE dynamic simulation, making it possible to run ESD checks at the full-chip level and use the results for signoff.

However, static checking has some limitations. For example, it doesn’t capture the correct triggering of dynamic ESD protection schemes, or the non-uniform current distribution through various fingers of a multi finger device.

One way to offset these limitations is to set very stringent limits for maximum allowed resistance for ESD paths. However, because designers must then increase the resources allocated towards ESD protection structures, this technique typically results in over-design, increasing the chip area or implementation of these ESD protection structures at the expense of functional IP.

Over-designing ESD protection circuits has other drawbacks, such as degraded performance due to additional capacitance and reduced signal-to-noise ratios. When designs have low margins, designers may need to further refine the results of the static checks to determine if failing the resistance criteria leads to actual device breakdown. Complementing the static checks approach with a solution that can help designers determine the exact voltages and currents on these devices with high fidelity enables them to accurately determine exactly where the design is with respect to the margins.

Context-aware SPICE flow

The Calibre PERC reliability platform [2] provides an innovative approach known as context-aware SPICE that brings together the best of both the static and dynamic approaches. Context-aware SPICE retains only the elements of the design that are necessary to be preserved for SPICE simulation, dropping those elements that are irrelevant to the SPICE simulation.

The input to the flow is a Calibre PERC rule deck containing topological checks to identify the different ESD structures, and point-to-point (P2P) rule checks to compute the resistance between devices to ports, pads, or bumps. Designers can use the Calibre PERC rule deck provided by the foundry, or the Calibre PERC packaged check solution [4], which contains a pre-written set of rules that can be easily configured for various kinds of design styles, process nodes, and foundries.

Designers input the pin pairs or input constraints (in the form of device breakdown voltages) for the paths they want to inspect.  Once designers launch the flow using Calibre PERC, it runs multiple steps (including an AFS run) and generates results (figure 3).


Fig. 3: Context-aware SPICE ESD simulation flow.

The flow provides multiple options for designers to view and debug the results. It creates a .tr0 waveform file, which the designers can load in a waveform viewer such as EZwave (figure 4).


Fig. 4: ASCII report and waveform files showing the peak voltage for a diode.

The Calibre PERC tool also writes out a database file that can be loaded into the Calibre RVE results viewer to enable designers to highlight the exact devices that are failing in the layout, and the resistances for various segments (figure 5). Designers can take advantage of the sophisticated debugging capabilities available inside the Calibre RVE interface to identify issues such as missing or inadequate vias or power grid straps.


Fig. 5: The Calibre PERC tool provides a database that can be used to debug the results of the context-aware SPICE flow.

The context-aware SPICE flow requires minimum setup, making it very easy to run. No designer intervention, partitioning, or approximations are required, providing deterministic results without the risk of introducing manual errors. Since this flow retains only the elements of interest, it can not only simulate small IPs, but also enable fast, accurate simulations at the full-chip level. Unlike traditional SPICE simulators, the AFS tool doesn’t experience convergence issues when simulating negative resistance or snapback behavior. Additionally, with the distributed processing capability of the Calibre PERC and AFS tools, various parts of the flow are run in parallel by using multiple CPUs on a single machine (multi-threading) and multiple CPUs on multiple machines (flexible multi-threading), making it possible to simulate multiple pin-pair combinations in a reasonable turnaround time.

With an innovative methodology like the context-aware SPICE flow, designers can overcome shrinking design margins while ensuring the fidelity of ESD analysis, overcoming the limitations of traditional ESD verification techniques.

Related paper link
https://resources.sw.siemens.com/en-US/white-paper-context-aware-spice-simulation-improves-the-fidelity-of-esd-analysis

References

  1. Recommended ESD-CDM Target Levels JEP157, JEDEC Solid State Technology Association. October 2009.
    https://www.jedec.org/standards-documents/docs/jep157
  2. Calibre PERC reliability platform, Siemens Digital Industries Software.
    https://eda.sw.siemens.com/en-US/ic/calibre-design/reliability-verification/perc/
  3. Analog FastSPICE platform, Siemens Digital Industries Software.
    https://eda.sw.siemens.com/en-US/ic/analog-fastspice/
  4. Hossam Sarhan, “Configurable-easy-to-use-packaged-reliability-checks,” Siemens Digital Industries Software. May 2019.
    https://resources.sw.siemens.com/en-US/white-paper-configurable-easy-to-use-packaged-reliability-checks


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