Copper Electrodeposition For Fan-Out Wafer-Level Packaging

How to deal with megapillar challenges in high density fan-out wafer-level packaging (FOWLP).


As integrated circuit designers bring more sophisticated chip functionality into smaller spaces, heterogeneous integration, including 3D stacking of devices, becomes an increasingly useful and cost-effective way of mixing and connecting various functional technologies. One of the heterogeneous integration platforms gaining increased acceptance is high density fan-out wafer-level packaging (FOWLP). Primary advantages for this packaging solution include substrate-less package, lower thermal resistance, and enhanced electrical performance. It is an example of more-than-Moore processing, where technologies other than pure Moore’s Law scaling help to provide greater integration and favorable economics.

Figure 1. Interposer structure in 2.5D packaging. (Lam Research)

Authors: Steven Mayer, Ph.D., Bryan Buckalew and Kari Thorkelsson, Ph.D. | Category: Technology

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