DAC 2023: Megatrends And The Road Ahead For Design Automation

As Silicon Valley is in the midst of the heat wave the world is experiencing, the recent Design Automation Conference and its exhibition discussed hot technologies. Three megatrends defined the current situation – artificial intelligence (AI), chiplets, and integration. To me, the more exciting aspect of DAC was the discussion of what is ahead for EDA in the decade to come, and for that, the keynotes and vision talks inspired but also gave no succinct unified clear answer in my mind.

Megatrend 1: Artificial intelligence

There are two facets here – Electronic Design Automation (EDA) enabling AI/ML chip and system development, and also how AI/ML is changing EDA and is potentially helping to solve the workforce problem by delivering productivity improvement we have never seen before over such a short timeframe in the 60-year history of EDA. Unsurprisingly, AI was everywhere in the exhibition and the conference with its research and engineering tracks. Wearing my corporate hat at Arteris, we had many discussions at our booth about enabling AI silicon and systems across various industries, including automotive and enterprise computing. The amount of data moving within and between AI/ML-related silicon is mind-bending, and Network-on-Chip (NoC) technology is a critical enabler. This year, I switched hats often, as I had the privilege to be part of the DAC Executive Committee to chair the IP Engineering Track. I gave an overview of the IP Track in “The Design Automation Conference Turns 60! What’s Hot? What’s Next?” The best presentation award this year went to HyperAccel’s “Latency Processing Unit (LPU) for Acceleration of Hyperscale AI Models,” a latency-optimized and highly scalable architecture that accelerates hyperscale models for Generative AI (e.g., GPT-3, LLaMA).

AI silicon is accelerating generative AI that writes code to accelerate AI silicon and software development—a fascinating loop.

Megatrend 2: Chiplets

For discussions about chiplets, one had to walk through many abbreviations and often confusing versions of heterogeneous integration. SiP/MCM, RDL, FOWLP, 2.5D-IC, 3D-IC, CoWos, UCIe, BOW, XSR, OHBI, AIP, 3DHI, how many do you know off hand? The only unanimous view about heterogeneous integration was its certainty. Whether one comes from the printed circuit board (PCB) side of the world, integrating various chiplets into one design, or from the world where the yield of very complex developments at the reticle limit dictates splitting silicon into smaller pieces from a cost perspective, it feels like Agent Smith holding down Neo on the subway track, waiting for the train to arrive and splatter them both, saying, “You hear that, Mr. Anderson? That is the sound of inevitability!” And with this significant transformation, design methodologies, chains, and dependencies will almost certainly look different a decade from now. We had many discussions about the proper NoC protocol support for die-to-die communication – CHI, CXL, CCIX… – and in the world of PHY technologies, the volume on UCIe seemed much louder than XSR, BOW, OHBI, and AIB. UCIe had an invited session in the IP Engineering Track, as well.

Megatrend 3: Integration

Challenges have been front of mind for system-on-chip (SoC) integration since the International Technology Roadmap for Semiconductors (ITRS) identified design cost as the major hurdle for semiconductor progress, and the industry talked about HW and SW design gaps.

Do you remember this chart?

Source: International Technology Roadmap for Semiconductors, 2011 Edition, Design

At the SoC level, the Accellera standard IP-XACT is the go-to format for topology definition. It is augmented by formats like CMSIS and SystemRDL and for register definition to drive hardware/software integration. There certainly was great interest in SoC integration capabilities on the show floor.

Of course, now we are entering an era in which classic SoC integration evolves into heterogenous integration using chiplets, and AI/ML is poised to help close the productivity gap. Integration challenges only grow, and we need to consider more and more non-electronic design automation aspects like thermal, electromagnetic, and mechanical. Fascinating times are ahead, for sure.

The road ahead

Judging from the keynotes, to me, the critical takeaway on the direction was how classic EDA – as defined and tracked in organizations like the Electronic System Design Alliance (ESDA) – is evolving further and interoperating with its adjacencies:

• Classic EDA interoperates with “system simulation,” considering thermal, mechanical, and electromagnetic interference effects. These effects make and break projects, especially when combining many pieces of silicon in a heterogenous fashion vs. on one SoC.
• Classic EDA connects to software development, especially for items that require close interaction between hardware and software – like security and safety.
• Classic EDA also gets closer to system environments comprising software and hardware, like product lifecycle management (PLM). The term “Digital Twin” was used often during the 60^th

Looking further ahead, I found Stanford Prof. Mark Horowitz‘s keynote “Life Post Moore’s Law: The New CAD Frontier Ahead” very inspiring. He augmented the classic graph showing why Moore’s Law is technically dead with a slide by Qualcomm that indicated that the commercial background at the core of Moore’s law – transistor cost scaling – had ended quite a while ago.

The technical and commercial end of Moore’s Law. Sources: Software-Defined Hardware Gains Ground — Again, Qualcomm ERI Workshop

Professor Horowitz then proceeded to call out chiplets as an intermediate solution only – because the transistor cost at very advanced technology nodes is still prohibitively expensive unless one has the volume – and suggested an app-store-like development concept that creates an open interface to hardware for everyone to use while maintaining a proprietary and revenue-generating platform underneath.

Bottom line: Fascinating jobs for the next decades. Let’s get to work!