Systems & Design

Debugging Point-to-Point Resistance Using Contribution By Layer In IC Validator PERC

Learn how IC Validator PERC includes all the needed capabilities for a point-to-point (P2P) resistance flow.


PERC Point-to-point resistance (P2P resistance) functionality is a crucial EDA technology to enable complex P2P effective resistance measurement along ESD paths in automation for foundry qualified ESD/Latch-up checker or in-house custom checker. This technology is applied to the entire chip, block, and IP designs on cell or transistor level layout database. Since the ESD path count could grow to thousands or even ten thousand, it is vital that the ESD path-oriented R extraction and distributed matrix solving capability has outstanding performance. This technology does not estimate P2P resistance using shortest or longest path schemes, but instead uses an accurate simulation focused on the critical layout polygons of ESD paths, including the P/G network. The P2P resistance measurement yields result in effective resistance (ohms) for each path measured. That result is a lumped resistance value reflecting all interconnect polygon layers between Source (current injection) and Sink (current Sink). Although the P2P resistance value gives users immediate information on how effective the ESD path behaves in discharging an ESD surge, a violated P2P resistance value alone is difficult for layout engineer to act on for any layout fix. When these checks fail, the resistance is reported for the failing source/sink pair, but a single resistance value does not guide how to fix it. A physical layer change will need to occur to fix it, but that single value provides no guidance on where to look and what to do, and that is especially problematic on complex paths that can span dozens of physical layers. Ultimately this can lead to design delays and even failing silicon.

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