Defect Detection Strategies and Process Partitioning for SE EUV Patterning

ABSTRACT
The key challenge for enablement of a 2^nd node of single-expose EUV patterning is understanding and mitigating the patterning-related defects that narrow the process window. Typical in-line inspection techniques, such as broadband plasma (291x) and e-beam systems, find it difficult to detect the main yield-detracting defects post-develop, and thus understanding the effects of process improvement strategies has become more challenging. New techniques and methodologies for detection of EUV lithography defects, along with judicious process partitioning, are required to develop process solutions that improve yield.

This paper will first discuss alternative techniques and methodologies for detection of lithography-related defects, such as scumming and microbridging. These strategies will then be used to gain a better understanding of the effects of material property changes, process partitioning, and hardware improvements, ultimately correlating them directly with electrical yield detractors.

INTRODUCTION
In recent years the semiconductor industry has made great strides in improving the resolution of EUV resist platforms to allow full entitlement of the optical resolution of the state of the art scanner technology. Chemically amplified resists, originally developed for 248nm lithography, have been adapted to EUV lithography and are now able to meet the resolution (<32nm) and dose (15mJ/cm²) requirements set in RLS (resolution, LER and sensitivity) performance goals for EUVL patterning readiness.^1-2 However, a key challenge for enablement of a 5nm node with single-expose (SE) EUV patterning is understanding and mitigating the stochastic defects that narrow the process window, ultimately leading to an effective limit in pitch resolution.

Stochastic failures arise from local fluctuations in photoelectric and chemical reactions that play a more dominant role as the number of features that can be printed with EUV reaches the trillions.³ For line/space (L/S) patterns these fluctuations can manifest as scumming that leads to increasing microbridges (MB) as lines widen when resist is underdosed, and as line breaks (OP) from variations in resist top loss as the lines thin when overdosed.^4-5 Figure 1 shows the MB and OP defect density at 30nm and 32nm pitch for a vertical L/S pattern printed at varying dose and measured post develop. At 32nm pitch the stochastic defect density profile remains flat for a dose range of approximately 2 nm at the experimental conditions. However, at 30nm pitch the MB count increases by roughly orders of magnitude. The MB defect density decreases exponentially with increasing dose and ultimately overlaps with formation of line breaks resulting in a lack of process window. This patterning cliff beyond which a structure of a given size will not have a defect-free window is thought to be a result of non-linearities of CD to dose close to the limit of resolution.³

Figure 1. a) Defect density of microbridges (MB) and line breaks (OP) measured post develop (e-beam inspection with coating using PTD-CAR resist on a dose stripe wafer) as a function of dose for 30nm and 32nm pitch L/S pattern. A patterning cliff at 30nm pitch is observed due to an increase in MB. b) Representative SEM images of the stochastic failures causing the patterning cliff (post etch).

A holistic SE EUV solution that overcomes stochastic defectivity at ‘prohibited pitches’ will require fundamental exploration of the patterning process space, starting from the layout, imaging and mask contributions. Resist properties, including optimization of quantum efficiency largely controlled by PAG content/type and EUV sensitizers, sensitivity, efficiency in solubility switching, dissolution properties during development, and component segregation will all play a role in stochastic defect modulation. Along with resist improvements, adhesion and interaction with underlayer, stack aspect ratio, hardmask type, and overall etch strategy and selectivity can also modulate or mitigate these type of defects. As we optimize materials and processes to minimize stochastic failures we also need to be cognizant of the effects the changes can have on yield due to inherent material defectivity, material interactions and interfacial effects, etch related defects CDU/LCDU, line edge and surface roughness, etc.

This paper will first describe the challenges in the detection of stochastic defects in L/S pattern, and lay out alternative strategies to understand stochastic yield limiters, exemplifying the analysis by comparing different resists. We will then focus on a methodology for assessing the stack contribution to non-stochastic defectivity as we explore new materials and modulate etch processes, as well as give a couple of examples of process improvements for their mitigation. We will finalize with a discussion of CDU control, and its importance for minimization of stochastic defects.

METHODOLOGY
A quad stack configuration was used for much of the L/S patterning described in this publication, containing a spin-on carbon underlayer in the range of 40-100nm, an inorganic hardmask with thickness <10nm, an adhesion layer to mediate interactions between resist and hardmask (5-10nm), and the EUV resist with thickness between 30-45nm. Patterning for experiments in Section 6 and 7 used a conventional trilayer resist paradigm, with a SiARC layer that was < 25nm in thickness. Evaluations were performed with L/S pitch features between 30nm and 36nm, patterned using an NXE3300B EUV scanner, and developed with 0.26N aqueous TMAH. Contact/hole patterns described in Section 6 had via sizes below 30nm. Hardware and process optimizations designed to improve defectivity and CDU, including new dispense systems, rinse and developer processes are described in the last two sections of the paper and references therein. Top-down images and CD metrology was accomplished using a VeritySEM 5i tool from AMAT. Electrical characterization was performed on the L/S BEOL structures range from 50um to 1 cm in length.

In addition to patterned exposures, dose meander, open frame exposures were performed to obtain contrast curves of different resist materials using an Aleris tool (KLA-Tencor) to estimate the remaining thickness after develop for a given dose.

Defect inspection on patterned wafer was accomplished using a Broadband Plasma 2915 tool and an eDR7110 electron-beam defect review tool, both from KLA-Tencor. After-develop inspections were also performed with an eP3 ebeam inspection tool from HMI for a subset of the experiments, in order to compare the sensitivity to the defects of interest using both techniques. Unless otherwise specified, the resist was coated with a thin, conformal inorganic film prior to ebeam inspection to decorate microbridge defects and improve their detection as described below.

Evaluation of in-film defectivity in different blanket patterning stacks was performed after coating or deposition of each layer, as well as after a specific timed etch, using laser-based (Surfscan SP3 from KLA-Tencor) and BBP inspection . At every step, a wafer was dropped for SEM review of a random defect sample (100/wafer) to obtain a defect pareto of the layer, while preventing the damage imparted by the SEM beam to alter defect detection downstream. This methodology can help to trace the source of defects through defect source analysis.

DETECTION OF STOCHASTIC DEFECTS POST DEVELOP
The first step to understanding modulations of stochastic defectivity is having a quantitative technique to measure the defects of interest. Partitioning at multiple inspection points is required to understand post processing steps that can mitigate or exacerbate the defects for best correlation to electrical measurements. However, detecting the defects post develop is key to deconvolve etch and lithographic contributions to better understand changes in EUV stack materials.

As potential yield-detractor defects continue to decrease in size with each node, inspection sensitivity is increasingly challenged, particularly post develop. The detection sensitivity of optical inspection post develop is often limited because photoresists are dielectrics with a low index of refraction that scatter little light, and are thus prone to having low signal for small defects.⁶ On the other hand, SEM-based defect detection techniques can suffer from local charging when imaging insulating films like photoresists, often leading to image distortion and deterioration of resolution. These limitations are demonstrated in Figure 2a, where we show the normalized defect density for a dose-modulated, 30nm pitch L/S patterned wafer inspected with an optical inspection system capable of scanning the wafer with wavelengths between 260-450nm. A slight increase in OP defectivity can be observed as the DCD space increases, but no sign of MBs throughout the DCD range probed. E-beam inspection of a similarly modulated wafer shows two to three times greater OP defect count at the largest DCD spaces with respect to optical inspection, and some MB detection that increases gradually as the trenches narrow. Comparison to electrical test measurements (Figure 2b) demonstrates not only shorts-limited yield at large DCD space, corresponding to the OP defects post develop that are detected with e-beam inspection, but also open-limited yield at the smallest DCD spaces, which should correspond to the MBs with extremely low capture rate detected with the same technique.

Figure 2. (a) Comparison of the detection sensitivity of optical (l>260nm) and e-beam inspection (no coating) for stochastic failures in a 30nm pitch L/S pattern as a function of DCD space (dose stripe wafer). The open red circles correspond to the OP defects captured with optical inspection (no MBs captured). E-beam inspection leads to a significant increase in OP capture rate and some detection of MB defects. (b) Electrical measurement of a corresponding wafer showing both short-limited yield at large DCD space due to line breaks, and open-limited yield due to MB at small DCD space. The data suggests a gap between both inspection techniques and electrical measurements.

The gap between after develop inspection readout for both inspection techniques and electrical testing needs to be addressed to advance solutions that reduce stochastic failures. One strategy we have developed is coating the resist with a thin, conformal, inorganic film. The film both serves to conformally decorate the MB defects to improve their detection, as well as curtail surface charging during e-beam inspection to prevent image degradation. Figure 3a demonstrates the improved MB detection sensitivity for a dose-modulated wafer, where a greater than 30 times increase in MB defect count is observed for the smallest DCD spaces with respect to an uncoated wafer. Representative SEM MB defect images from inspection of uncoated and coated wafers also demonstrate decreased blurriness in the latter condition. The coating partially compromises the capture rate of line breaks (~0.5 times OP defect count at the largest DCD spaces probed) as a result of masking or healing of line notching by the film deposited (Figure 3b). Nonetheless, if the OP sensitivity is found to be insufficient in the coated condition, partial inspection of the wafer before coating can be performed to target OP defect detection.

Figure 3. Improvement in MB detection post develop obtained by coating resist with conformal inorganic film and inspecting with e-beam. (a) Comparison of MB capture rate between coated and uncoated 30nm pitch L/S patterned wafer as a function of DCD space (dose stripe) demonstrating a significant increase in MB detection. The inset shows corresponding SEM images of MB in both conditions. (b) OP capture rate decreases slightly when coating the wafer due to partial masking of notches on the line by deposited film.

The use of thin film defect decoration for enablement of MB detection post develop has allowed us to predict the downstream effects of changes in lithographic conditions. This is exemplified in Figure 4, where we compare the OP and MB defect density of 30nm pitch L/S patterned wafers with two different resist thicknesses as a function of DCD space to try to assert changes in location and modulation of the defect process window. E-beam inspection post develop suggests the minimum in defect density lies around 13.5nm to 14nm DCD space (Figure 4a and b).  Accordingly, we see a shift in the position of the minimum within the wafer for the thicker film since exposure conditions were not adjusted to center the film to a target DCD. The inspection also suggests the OP defect count is reduced when the resist thickness is increased, in accordance with our expectations. Inspection of replicate wafers post etch demonstrate good agreement with the post develop e-beam data (Figure 4c and d).

Figure 4. Demonstration of enablement of process window characterization post develop through e-beam inspection by coating wafers before scan. (a) and (b) Comparison of e-beam inspection of 30nm pitch L/S patterned wafers as a function of DCD space (dose stripe) for two resist thicknesses show the shift in the position of the minimum within the wafer (same exposure conditions in both) and a decrease in OP defect density for the thicker film. The graphs in (c) and (d) contain optical inspection results for replicate wafers scanned post etch. (e) and (f) Corresponding electrical measurements demonstrate good agreement between both inspection techniques and electrical data.

Electrical testing further confirms the shift in process window position for the thicker film, as well as a slight improvement in overall yield due to suppression of shorts (Figure 4e and f). However, the center of the electrical process windows for both conditions is slightly shifted towards lower exposures with respect to the defect process windows predicted by either inspections. This may be due to underestimation of line breaks at both inspection points. In the previous section we discuss how the coating used to allow MB detection can partially compromise the capture rate of line breaks. This can be remedied by performing inspections without the coating to target OP defects. Recent data using ebeam inspection post etch has also shown improved capture rate for OP defects with respect to optical inspection, giving a path for improved correlation between inspection and electrical evaluation.

It is important to stress that our main metric for overall process improvement is post etch inspection, which is facilitated by the much improved defect signal from our TiN patterned hardmask when inspected with an optical system, as well as reduced charging and damage from e-beam inspection that allows more aggressive imaging conditions for this layer. Additionally, the inorganic coating used for this study is destructive, preventing further processing of the wafer for a better understanding of defect transfer through etch and electrical testing. Nevertheless, the value of enabling post develop inspection is in allowing fast upstream defect characterization of incoming lithography for resist and stack material screening, as well as for process window centering without convolution with etch contributions.⁷

Ultimately, the availability of inspection tooling with the necessary detection sensitivity for the stochastic defects at play would be necessary to ensure defect levels that are compatible with a high volume manufacturing process. Electromagnetic simulations were conducted by KLA-Tencor to understand defect detectability and signal strength of a 13nm full height protrusion defect on a 36nm pitch L/S pattern with an 18nm line post litho as a function of wavelength and imaging mode. In this case, a resist/SiARC/OPL trilayer stack on SiN was used to set up the 3D Coventor model. The wavelength-based analysis shown in Figure 5 demonstrates a substantial increase in signal strength at short wavelengths (below 230nm). Additional work to better understand the detection sensitivity to the defects of interest is currently being conducted on wafers using a 39xx KLA-Tencor system that allows optical inspection at wavelengths below 230nm.

Figure 5. Simulation of the signal strength from a 13nm protrusion defect on a 36nm L/S pattern (18nm line) post develop, assuming an EUV PTD-CAR resist/SiARC/OPL trilayer stack on SiN. The curves represent the data for the two inspection apertures with best sensitivity. The electromagnetic simulation suggests improved signal strength at shorter wavelengths.

UNDERSTANDING RESIST DISSOLUTION CONTRIBUTION TO MICROBRIDGE DEFECTIVITY
Much interest is being paid to factors that contribute to noise in the solubility switch and development properties of a resist matrix and their role in microbridge defectivity. ⁵

The development of nanoscale roughness during resist dissolution has been extensively studied in the past 20 years in the hopes of gaining a fundamental understanding of contrast profiles and line-edge roughness modulation.^8-10 The molecular basis of roughness has been probed by application of the critical ionization model to resist dissolution. This model has correctly predicted the relationship between roughness and dose, which leads to low resist surface roughness at low doses (or high degrees of blocking), passes through a maximum and then decreases again at high doses where the degree of deprotection increases.⁸ This is clearly illustrated in experimental data from Goldfarb and Kumar¹¹ for an EUV CA resist on an HMDS-primed silicon substrate reproduced in Figure 6. AFM roughness measurements show the expected peak in roughness as a function of dose for a dose meander wafer. It also demonstrates the resist develops in a highly non-uniform fashion with large and persistent aggregates (~20nm in height). The authors suggest that the extremely thin resist films used in EUV stacks may lead to confinement of the polymer chains near the substrate, causing deviations from bulk properties.

Figure 6. Dependency of surface topography (AFM) on dose (data from reference 11). The contrast curve wafer has a commercial EUV CAR resist exposed with EUV scanner NXE3300B. The images show residual resist develops in a highly non-uniform fashion showing persistent large aggregates at high doses.

The relationship between LWR/LCDU and microbridge defectivity has also started to be examined.^1,1,5 It has been shown that although there is some degree of correlation between LWR and microbridge failure, LWR is not a good predictor of MB defect count as the former parameter saturates at a constant value, a phenomenon that is not seen for MBs.⁵

Within this context, we studied the dissolution properties and microbridge defectivity of three resists sharing the same platform but varying in base quencher loadings (Table 1). Figure 7a shows the contrast curves from dose meander open frame exposures of the resists on a primed silicon substrate (HMDS). The expected decrease in photospeed with increased base quencher amount is observed. However, an increased footing is observed for resist A, suggesting residual material remaining beyond the clearing dose. The same three resists were coated on an organic underlayer and exposed as a dose stripe, forming L/S features of 30nm in pitch. Post develop inspection facilitated by film deposition (Figure 7b) suggests inferior microbridge performance for the resist with the lowest dose-to-size (resist A), a trend that has been reported elsewhere.⁵ However, little difference is observed in the degree of defectivity of resist B and C, despite the increased quencher loading of the latter, suggesting that microbridging cannot be solely addressed by photospeed slowdown.

Table 1. Comparison of quencher loading and sensitivity for three PTD-CAR resist sharing same platform

We further probed the inhomogeneities of each resist through dissolution by inspecting the dose meander wafers described above for aggregate counts. The relationship between aggregate count and dose also shows a maximum in defect count, then decreases close to the clearing dose (Figure 7c). Interestingly, resist A shows a much broader non-uniformity dissolution window than the slower resists (resists B and C), both of which demonstrate an aggregate distribution with relatively similar breadth and height. It is important to point out that a low level of aggregates persist even beyond the clearing dose for all resists. Further investigations are being conducted to understand if these inhomogeneities are indeed correlated to the microbridge defectivity trends observed.

Figure 7. (a) Contrast curves for the three resists in Table 1 show expected decrease in photospeed with base quencher loading increase. (b) MB defect density measured post develop with e-beam inspection (coated) for a 30nm pitch L/S pattern and plotted as function of DCD space for the three resists. The resist with the lowest dose (A) shows decreased MB performance, but no difference is seen between resists B and C. The inset shows the logarithmic plot demonstrating the trend observed is consistent throughout the DCD range studied (c) Dependency of aggregate count with normalized dose suggests broader non-uniformity regime for the fastest resist (A), while similar distributions are seen for resist B and C. All three resists show persistent aggregates beyond clearing dose.

Overall, these experiments highlight that a better understating of how to modulate stochastic defectivity will require improved methods that allow detection of the defects of interest after develop for rapid screening, as the ones outlined in the previous section of the paper, but may also benefit from alternate approaches that help us understand the role of inhomogeneities and substrate-resist interactions on defectivity.

NON-STOCHASTIC DEFECTIVITY ASSESSMENT THROUGH PROCESS MODULATION 
As we explore the patterning parameter space to modulate stochastic defectivity, the new processes and materials being tested can have an effect on non-stochastic defectivity that could ultimately impact yield. It would be ideal to assess the defect contribution of each material in the stack through process modulations.

In a previous publication,¹² we described the down selection and optimization of EUV patterning hardmask material candidates through a comprehensive layer-by-layer defectivity evaluation of the blanket films in the stack that was able to capture detrimental material interactions and process anomalies. We expand on this concept by considering the effect of the etch processes used for patterning the stack in blanket film defectivity. This is achieved by performing a layer-by-layer blanket inspection of the EUV stack followed by varying timed etches on the film being tested. In-film defectivity will evolve through etch depending on the chemistry of the defect and likely be etched away completely with sufficient over etch, giving us a process window for the persistence of the defect. Thus, this window will give us a better idea of the contribution of in-film defectivity as we modulate our process to inhibit stochastic defects.

An example of the methodology is shown in Figure 8a, where we plot the in-film defectivity of the organic adhesion layer coated on the hardmask material of one our candidate stacks as a function of etch time. Defect source analysis allows us to isolate the defects native to the adhesion layer and track them through etch. The normalized defect counts initially increase with increasing etch time and then decrease as we etch away most of the defects in the film. The initial increase in defectivity is likely due to the uncovering of the embedded defects as the film is etched (Figure 8b).

Figure 8. Etch process window of defects in the adhesion layer of an EUV stack (blanket defectivity). (a) The plot shows an initial increase in defect count with etch time as in-film defectivity is revealed, followed by a decrease as defects are reduced in size with etch. This process is illustrated in (b).

Qualitatively similar results can be obtained from a SiARC hardmask layer coated on OPL (Figure 9a). However, in the case of SiARC the modulation through etch is more significant, expanding several orders of magnitude. Similar experiments were performed for a thin aSi hardmask layer on OPL (Figure 9b). A partial etch of the film, which contains a descum step, reveals the existence of pinholes that were not detected on the blanket film prior to etch. Inspection of an etch-only control wafer without the descum reveals no pinhole defects, whereas a control wafer with descum only shows a significant increase in pinhole count. We propose that the descum step is capable of enlarging the pinhole defects present in the aSi film, allowing this challenging defect type to manifest. Using etch strategies to detect pinholes in EUV stack films needs to become a routine practice since the films used as hardmask and adhesion underlayers are being thinned down to dimensions where pinhole formation is more likely to happen.

Figure 9. (a) Etch process window for in-film defects in a SiARC layer on top of an OPL layer, showing significant modulation of defect count through etch. (b) The partial etch (with a descum step) of an aSi thin film on OPL allows detection of pinholes in the hardmask. In an etch-only control no pinholes are detected, while a descum-only control shows large amount of pinholes, suggesting the descum step is enlarging an existing defect by etching the OPL layer.

PROCESS IMPROVEMENT FOR MITIGATION OF NON-STOCHASTIC FILM DEFECTIVITY
After defining a strategy to reveal how in-film defectivity will evolve through etch modulation, the next step is to understand how the defects will affect the patterned wafer and to find strategies to mitigate them. In the past few years we have been working on systematic improvements of coating hardware and process optimization to combat defectivity of EUV layers.^12-14 Two examples of our continued effort are discussed below.

In the first example, we tested a new dispense system (NDS) designed to mitigate embedded defectivity in EUV films. The NDS was applied to both an OPL and SiARC layer used to pattern 36nm pitch L/S content, and compared to our current dispense system. After develop inspection showed no statistically significant difference between the two conditions, as is often the case with small defects embedded in lithographic films (not shown). However, after etch inspection revealed a 37% reduction in total defect count when using NDS, as seen in Figure 10a. The defect pareto shown in Figure 10b demonstrates that the improvement comes from reduction of embedded defects, as expected, and indicates that the primary defect in the NDS processed wafers is MBs. The data illustrates the importance of improving baseline defectivity to be able to focus on mitigation of stochastic defects. It also highlights the increased need to rely on after etch inspections in detection of lithographic defects, as discussed in Section 3. This will become increasingly true as the size of the potential yield detractors continues shrinking in relative proportion to the pitch.

Figure 10. (a) Normalized post etch defectivity from 36nm pitch L/S patterned wafers, comparing the use of our current dispense system for the OPL and SiARC layers to the NDS. A statistically significant reduction in defectivity is observed when using NDS. (b) Comparison of the defect Pareto for the two conditions, demonstrating that the improved defectivity performance of NDS is related to a reduction in embedded defects.

In the second example we look at optimizing the rinse process to improve process-related defectivity. EUV resists have been shown to have a higher contact angle than immersion resist, even post develop.¹⁵ Their increased hydrophobicity makes it difficult to reduce water droplets remaining from the rinse and dry-spin processes, leading to residue defects. We test two optimized rinses in a contact hole pattern and compared them to our current rinse process with post develop inspections. The results show a 90% decrease in total defect counts for one of the optimized processes (Figure 11a) due to a reduction in residue and stain-like defects, such as the ones depicted in Figure 11b.

Figure 11. (a) Defect reduction observed on a contact hole pattern using developer rinse processes optimized for increased hydrophobicity of EUV resists. (b) Representative images of the residue defects mitigated with the optimized rinses.

CDU CONTROL FOR PROCESS STABILITY
Global CDUs need to be improved as we move toward an EUVL manufacturing phase. Stochastic defectivity puts an additional pressure on CD control because, as discussed previously, small CD variations can lead to a significant increase in stochastic failures, particularly as we push to smaller CDs. Optimization of the developer process is key to achieving better CDU control.

Figure 12a and b show the CD profile across the wafer for dense L/S and iso trench pattern, respectively, for our current developer process. A systematic signature in the global CDU is observed using this process, wherein the CD near the center of the wafer decreases significantly. The opposite is true of the iso trench profile. We evaluated two different optimization schemes of the developer process, both of which show a more constant profile across wafer, with the best process displaying an 84% decrease in CD range across wafer for dense L/S pattern, and a 54% decrease for iso trench pattern (Figure 13a).  Similarly, the 3-sigma CDU across wafer values, calculated relative to the target CD, decreases from 3.5% for the current developer process to 2.7% with the optimized developer process for the dense L/S pattern (Figure 13b). These types of CDU improvements will be crucial for EUV manufacturability.

Figure 12. Comparison of the CD profile using our current developer process and optimized processes for (a) dense L/S pattern and, (b) Iso trench pattern.

Figure 13. (a) Improvement in CD range across wafer for both dense L/S pattern and Iso trench pattern using optimized developer processes. (b) Similar improvement in 3-sigma CDU values across wafers is shown for the dense L/S pattern.

SUMMARY
Stochastic defectivity will be one of the key challenges to overcome as we look towards a 2^nd node of single-expose EUV patterning. Mitigating stochastic defects will require in-line techniques that are capable of detecting these yield detractors post develop. In this paper, we discussed techniques and strategies for detection of stochastic defects in dense L/S patterns post develop. Simulation work was also performed as a starting point to understand if state-of-the art optical inspection systems capable of inspection at shorter wavelengths will improve detection of stochastic defects. Further work is underway to assess detection capabilities of this tooling on wafer.

The inspection strategies developed have enabled the exploration of resist properties that can improve the MB performance. Our results show that microbridging cannot be solely addressed by photospeed slowdown, and suggest a possible link to dissolution inhomogeneities during resist development that needs to be explored further.

Additionally, we proposed a methodology to assess the in-film material contribution to non-stochastic defectivity, and its modulation through etch, as we explore new materials for EUV stacks. We then described specific examples of hardware and process optimization than can inhibit in-film and process defectivity important for EUVL manufacturability. Finally, we also described an optimized developer process that allows better CDU control, required to meet global CDU targets and reduce stochastic defectivity.

ACKNOWLEDGMENTS
This work was performed by the Research Alliance Teams at various IBM Research Facilities. The authors would like to thank Dario Goldfarb, Peggy Lawson, Dan Corliss, Martha Sanchez, Genevieve Beique, and Hoa Truong for experimental support and helpful discussions.

Authors: Luciana Meli¹, Karen Petrillo¹, Anuja De Silva¹, John Arnold¹, Nelson Felix¹, Chris Robinson¹, Benjamin Briggs¹, Shravan Matham¹, Yann Mignot¹, Jeffrey Shearer¹, Bassem Hamieh¹
Koichi Hontake², Lior Huli², Corey Lemley², Dave Hetzer², Eric Liu², Ko Akiteru²
Shinichiro Kawakami³, Takeshi Shimoaoki³, Yusaku Hashimoto³, Hiroshi Ichinomiya³, Akiko Kai³, Koichiro Tanaka³
Ankit Jain⁴, Heungsoo Choi⁴, Barry Saville⁴, Chet Lenox^4
1IBM Semiconductor Research, 257 Fuller Road, Suite 3100, Albany NY, USA 12203
²Tokyo Electron Limited, Technology Center America, LLC, 255 Fuller Road, Suite 214, Albany NY, USA 12203
³Tokyo Electron Kyushu Limited, Fukuhara 1-1, Koshi, Kumamoto, Japan, 861-1116
⁴KLA-Tencor at Albany Nanotech, 257 Fuller Road, Albany NY, USA 12203

Originally published in SPIE Advanced Lithography. Luciana Meli et al, “Defect detection strategies and process partitioning for SE EUV patterning,” Proc. of SPIE Vol. 10583 105830E-17 (2018).

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