Deriving Configuration Time For eFPGAs

Part 1 of this blog post described how to configure an eFPGA, using Achronix’s Speedcore eFPGA as an example. It explained why each instance of the eFPGA in an ASIC or SoC design must be configured after the system powers up due to its nonvolatile SRAM technology to store configuration bits.

This post will detail how the configuration time is derived, once again using Speedcore eFPGA as the example.

To begin, the time required to program a bitstream depends on the configuration mode being used, the data width, clock frequency, and of course, the size of the configuration bitstream. Configuration steps include:

• Clearing the configuration memory
• Configuration bitstream programming
• Additional control state transitions to sequence resets and to switch the eFPGA from configuration mode to user mode

As a refresher, the Speedcore eFPGA’s FPGA control unit (FCU) handles all three. The time required to execute these tasks depends on many factors, especially in the three configuration modes: Serial Flash (SPI), CPU, and JTAG. The FCU’s configuration-mode pins along with a register-based setting in the JTAG controller select the configuration mode.

In the CPU and JTAG configuration modes, the eFPGA acts as a slave and accepts a programming clock in addition to commands and configuration data from the CPU or the JTAG master. In Serial Flash configuration mode, the eFPGA acts as a master and supplies a clock to the attached to a single SPI serial NOR flash memory (for the x1 flash configuration) or to four flash memory ICs (for the x4 flash configuration).

Calculating the configuration programming time
Bitstream programming time dominates other task-execution times for the CPU and Serial Flash configuration modes, which makes estimating the configuration time for these modes straightforward.

Calculating the configuration programming time for these two modes is done with the equation –– (the number of bits being programmed / data width) × clock period –– to produces a configuration-time estimate. The required configuration time in CPU mode may depend on software drivers and the interface used. Also, note that the JTAG configuration mode incurs additional JTAG protocol overhead, increasing the configuration time.

The data width variable in the equation varies with the implementation of the eFPGA in the ASIC or SoC. For the CPU configuration mode, the bit width can be 1, 8, 16, 32 or 128 bits. For the Flash configuration mode, the bit width can be either 1 or 4 bits wide. The maximum clock rate for both of these configuration modes is 100 MHz, which makes the minimum clock period 10 nanoseconds.

One final factor to complete the equation is the number of configuration bits to be programmed. A conservative estimate puts the number of configuration bits in a Speedcore eFPGA at 40 million configuration bits for 100K LUTs.

Rolling these factors together produces a table (see below) showing estimated worst-case configuration times.

Table 1: Estimated Worst-Case Configuration Times for Speedcore eFPGAs (Estimated times are in milliseconds and assume a 100MHz clock)

The table shows estimated worst-case times, though typical configuration times should be about 30%-40% lower than the worst-case times listed in the table.

In all but one case for the largest configuration, as shown in Table 1, the Speedcore eFPGA requires less than one second for configuration. The maximum bitstream configuration data rate in the CPU configuration mode with a 128-bit parallel interface running at 100 MHz is a brisk 12.8 Gb/s, which results in configuration times of less than 10 milliseconds. Consequently, using a 128-bit parallel interface will offer the fastest configuration time from the CPU configuration mode.

More detailed configuration bitstream sizing equations appear in the Speedcore Configuration User Guide (UG061).