Design Process And Methodology For Achieving High-Volume Production Quality For HDFO Packaging

Ensuring an IC package will meet manufacturability and performance requirements.


Unlike the traditional system on chip (SoC) design process, which has fully qualified verification methods embodied in the form of process design kits (PDKs), chip design companies and outsourced semiconductor assembly and test (OSAT) suppliers have typically had no integrated circuit (IC) package co-design sign-off verification process to help ensure that an IC package will meet manufacturability and performance requirements. Package die are often produced using multiple processes and multiple foundries, which not only raises the level of complexity, but also increases the need for a process that can ensure these disparate products can be manufactured within a single package.

Without Amkor’s SmartPackage PADK, package designers are at a significant disadvantage designing High-Density Fan-Out (HDFO) packages compared to their IC design counterparts for chip design. IC designers can use the verified process design kits (PDKs) from the foundries to not only reduce their risk, but also to greatly improve their overall productivity by implementing known, repeatable, proven verification techniques. The lack of formal HDFO verification processes for package designers means they must work with documented rules that are dependent on interpretation and/or differing processes each time they submit a package design to a substrate manufacturer. In addition, the new HDFO class of packages now coming into the market merge the interactions between the redistribution layers (RDLs) and the silicon, so there is no clear separation between the traditional die and package, necessitating a unified co-design flow.

Why can’t existing verification flows be used?

There are multiple reasons why traditional IC-centric physical verification solutions do not work for package verification. From a physical checking perspective, IC-centric verification tools rely on GDSII or similar layout formats for their inputs. Because these formats contain no information about a geometry’s placement in the vertical direction, that information is typically inferred through layer mapping. From this kind of layer mapping and the use of typical layer-naming conventions, it can be inferred, for example, that metal2 is vertically higher than metal1 and lower than metal3, and the layers’ electrical connectivity can be established through the presence of appropriate via layers. All geometries mapped to the same layer by way of a data type designator are considered coplanar. Geometries on the same layer that overlap or abut are treated as if they are, in fact, a single polygon, as they will be merged during the mask generation process.

This assumptive process breaks down in any kind of package where multiple processes are involved. Consider even the simplest case of a single die in a wafer-level package that is connected to the ball grid array. If the traditional method of layer mapping is used, it would have to ensure that the redistribution layer (RDL) routing in the package never conflicts with a layer used by any die that may be placed in the package, a practice that is nearly impossible, because the die can come from any foundry or fab and can be produced at any process node. There is generally little to no commonality in layer mapping from one foundry to another, and in some cases, even from one node to another at the same foundry. However, without this assurance, the design rule checking (DRC) tool interprets the geometries located on the same layer as the geometries from the package RDL as co-planar and considers those geometries as if merged, when, in reality, there is a significant vertical displacement between them.

Why HDFO needs a formal package assembly design kit (PADK)

The purpose of a “package assembly design kit” is like that of an IC foundry’s process design kit—to ensure manufacturability and performance using standardized rules that ensure consistency across a process. An assembly design kit could provide many benefits to the industry: reduced risk of package failure, reduce redesign cycles, increased packaging business opportunities and increased use of advanced IC packages.

What would a PADK look like?

So, what should such a PADK include? Obviously, it must include both a physical verification and an extraction signoff solution. A verification engineer must be able to verify each item independently and at the interfacing level (die-to-die, die-to-package, etc.). All these processes should be independent of any specific design tool or process used to create the assembly. In addition, a complete PADK must work across both IC and packaging domains, implying that the flow must support multiple formats. Finally, all these verification processes must be validated.

But a PADK is much more than just the signoff requirements. Package designers need validated technology files for their design creation tools; these files are created as part of the development of a detailed reference flow for Amkor’s HDFO technology process.

Is a PADK practical?

A PADK can prove the feasibility of a physical verification solution that enables packaging rules that are independent of any specific package design or die process. The initial steps included the definition of requirements and responsibilities, followed by the development of specific checks and flows. The goal was to create a method for presenting a fully stacked system that included both DRC and LVS performed on each element independently and at the interfacing level, as well as support for assembly checking.

Defining requirements and responsibilities

Amkor accepted the responsibility of writing the design rules that defined what the assembly should look like. The first item to determine was: what was needed to perform design rule checking and layout versus schematic (LVS) comparisons on packages. Design rules had to be created that addressed package-specific requirements. For example, rules were needed to govern the design of trace connections in the package, including specifics such as size, distance, etc. One issue is package trace widths can vary depending on whether they are over die, between die, or completely outside the die.

What are the results?

Does a PADK work? Yes, a rule file for a proprietary HDFO process has been created. This rule file can be used by companies who target this package technology at Amkor, regardless of what process nodes the dies are, or how many dies are in the package. The rule file checks the manufacturing constraints of the package RDL and the die-to-die constraints and verifies the connectivity through the package from die-to-die and die-to-BGA. Amkor now makes this rule file available to customers leveraging their HDFO packaging technology to support multi-die integration.


A PADK provides a standardized process to ensure the manufacturability and assembly of advanced IC packages. While creating a PADK is a non-trivial effort, using a PADK can reduce risk of package failure, while also reducing turnaround time and ensuring a high-volume yield result. By implementing a standardized, proven process, companies can improve both their first-time success rate and overall product quality.

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