中文 English

Thermal Simulation Of DSMBGA And Coupled Thermal-Mechanical Simulation Of Large Body HDFO


Electronic packaging has continued to become more complex with higher device count, higher power densities and Heterogeneous Integration (HI) becoming more common. In the mobile space, systems that were once separate components on a printed circuit board (PCB) have now been relocated along with all their associated passive devices and interconnects into single System in Package (SiP) style suba... » read more

Wafer Level Void-Free Molded Underfill For High-Density Fan-out Packages


In this study, experiments and mold flow simulation results are presented for a void-free wafer level molded underfill (WLMUF) process with High-Density Fan-Out (HDFO) test vehicles using a wafer-level compression molding process. The redistribution layer (RDL)-first technology was applied with 3 layers of a fine-pitch RDL structure. The test samples comprised 11.5 x 12.5-mm2 die with tall copp... » read more

Chip-Last HDFO (High-Density Fan-Out) Interposer-PoP


Interposer Package-on-Package (PoP) technology was developed and has been in very high-volume production over the last several years for high-end mobile application processors (APs). This is due to its advantages of good package design flexibility, controllable package warpage at room temperature (25°C) and high temperature (260°C), reduced assembly manufacturing cycle time and chip-last asse... » read more

Design Process And Methodology For Achieving High-Volume Production Quality For HDFO Packaging


Unlike the traditional system on chip (SoC) design process, which has fully qualified verification methods embodied in the form of process design kits (PDKs), chip design companies and outsourced semiconductor assembly and test (OSAT) suppliers have typically had no integrated circuit (IC) package co-design sign-off verification process to help ensure that an IC package will meet manufacturabil... » read more

Heterogeneous Integration Using Organic Interposer Technology


As the costs of advanced node silicon have risen sharply with the 7 and 5-nanometer nodes, advanced packaging is coming to a crossroad where it is no longer fiscally prudent to pack all desired functionality into a single die. While single-die packages will still be around, the high-end market is shifting towards multiple-die packages to reduce overall costs and improve functionality. This shif... » read more