Designer And IP Tracks Swell With Focus On ML, Security And Traditional EDA Methodologies

What are designers keenly interested in as the 57^th Design Automation Conference (DAC) approaches? If you said machine learning (ML), you’d be only partially right.

Based on designer and IP tracks submissions to the 57^th edition of the venerable electronics-industry event, ML – how to design with it and optimize EDA tools and flows using it – is a hot topic. But so too are more traditional avenues of exploration for practicing designers, such as physical design, abstraction, verification, security and the evolution of IP design.

“ML is exploding. That’s a definite trend. This is closely followed by open-source architecture, and IP security is becoming an increasing concern,” said Designer Track Co-Chair Ambar Sarkar of NVIDIA.

Paper submissions also reflected breakthroughs and insights into an increasing complex design flow, according to IP Track Co-Chair Randy Fish of UltraSoC.

“It’s the question of how to define a system,” he said. “You’re seeing multi-die solutions so there’s a session on die-to-die connection. The energy used to communicate between die is reaching fundamental limits. With some ML applications you’re starting to see creative packaging and, in some cases, full wafer solutions. That makes people rethink the problem at a system level.”

This year, overall submissions to the designer and IP tracks rose 15% over last year, continuing a steady three-year rise: 160 paper submissions in 2018, 170 in 2019 and this year 197.

But clearly the interest most on the minds of designers is ML.

“We are not just designing chips. We are looking at the whole flow, from concept to GDS2,” said Designer Track Co-Chair Natarajan Viswanathan of Cadence Design Systems. “Big companies are looking at the flow from top to bottom. At each point, how can ML improve their impact? On IP side, how can we improve the portability of the IP using ML technology? We have talks targeting that. ML is exploding at not just the edge but how you use it in-house. It’s becoming more democratized because more and more people feel empowered to use ML engines and apply them.”

He added that papers submissions around ML aren’t focused on data analysis as much as they are around how ML can be applied to the design in chips.

“What are architectures and hardware approaches required for those ML apps?” he said.

Fish said ML is becoming a fundamental tool in the toolbox.

“You used to have to learn PERL, and Tcl and Python, and now if you’re not well versed in using ML techniques you’re going to be behind the curve, not only in chip design but in the EDA community,” he said.

Designer/IP Program Chair Renu Mehra of Synopsys, Inc. said submissions also reflected intense interest in open-source design around RISC-V and ultra-low-power design. In addition, submissions reflect insights on security and functional safety in automotive systems, as well as system-level design insights.

Said Sarkar, “We’re trying to bring in concepts about how to design at something higher than clock level. Also, when does formal design break out? The level of expectations of what you get out of it is higher every year. Simple thought problems won’t do any more. People want to know how we solve the hard challenges.”

Viswanathan said, “I think we did see an uptick in back-end power and timing methodologies. Power still a trend. We had more submissions there, especially in timing power signoff. What are challenges and optimizations? A lot more focus on power-related stuff. That increased a lot in terms of submissions.”

What’s behind the recent surge in paper submissions and the leading-edge insights that will be presented this year?

Transformation, the chairs agreed. Whether it’s ML’s potential impact, open source design or the heightened importance of security inside IP and systems, the design industry is entering a new, robust era.

“There’s good growth,” Fish said. He added that while in years past much of the paper topics were focused on incremental designs on previous generation recent years have seen an explosion in clean-sheet designs.

“ML has driven these clean sheet, large die, complex designs. People are asking ‘how should we approach this problem?’”

The 57^th DAC runs virtually from July 20-24 and will be available on-demand until August 1.  Registration is now open, please visit DAC.com and register today!