Detecting Electrical Hazards Incurred By Inter-Voltage Domain Crossing In Custom SRAMs

Fast-growing markets, such as 5G, biotechnology, AI, and automotive, are driving a new wave of low-power semiconductor design requirements and, hence, more aggressive low-power management techniques are needed. Consequently, even large macros within a chip, such as SRAMs, now feature multiple voltage domains to limit power draw during light-sleep, deep-sleep, and shutdown-low-power modes. These modes introduce logical plus electrical complexity which drives the need for ESP formal equivalence checking during design and verification. Many tier one semiconductor companies have extensively used ESP to verify their memory macros.

ESP’s symbolic simulation technology verifies the equivalence between reference and implementation models with high design coverage. ESP performs this verification in different design representations e.g. Verilog versus SPICE/schematic netlist, Verilog versus Verilog (e.g. behavioral Verilog to RTL), Liberty-compiled DB versus Verilog or SPICE/schematic netlist. ESP works at native transistor level without abstraction and supports planar, FDSOI, FinFET and Gate-All-Around silicon technologies. With a formal equivalence checking engine under its hood, ESP verifies the equivalence between the models with a few automatically generated symbolic vectors, providing high design coverage and enabling customers to catch hard to find corner case design bugs.

More recently, customers have started using ESP’s Power Integrity Verification (PIV) mode to validate the power domain interfaces in their custom memories. ESP PIV detects common low-power and power-down errors and generates SPICE vectors for analysis and debug. With its ability to detect electrical errors during a myriad of the light-sleep, deep-sleep and shutdown-low-power mode scenarios, ESP PIV has seen increased customer adoption in recent years. Power integrity verification mode uses dynamic symbolic vectors to unearth corner case power issues that complement standard static power checkers. These capabilities include detection of:

1. Missing/incorrect level shifts
2. Missing/incorrect isolation circuitry
3. Power/ground shorts
4. Sneak paths between supplies

An example of the high value of ESP’s Power Integrity Verification was recently seen during the silicon validation of a customer’s testchip. When powering up their testchip, the customer sequenced the ramp-up of the different voltage supplies for the power domains on the chip and noticed a large unexpected current draw. Having deduced the issue as originating from one of the large memory macros, the customer ran ESP PIV on this design. To replicate the power up sequence, they enabled the tristate power supply option in their run scripts and observed ESP detecting the power draw that had escaped their initial testing. This not only exposed the incorrect ramp-up sequence in the simulation itself, but also showed an alternative safe power-up sequence prior to the production chip tapeout.

Convinced of the value of detecting all possible power domain ramp-up sequences by allowing the tool to apply different voltages to the power supplies in each domain and also accounting for the possibility the supplies could be floating/tri-stated, ESP PIV has found wide deployment with this customer. This success has expanded the ESP footprint from just memory teams to all custom circuit teams at this customer including analog/mixed-signal and SERDES teams.

Using ESP’s functional verification for mission-mode equivalence checking and power integrity verification for electrical checks gives memory IP designers a powerful and much needed capability to verify a large number of scenarios and modes efficiently with just a few symbolic vectors.

You can learn more about the about ESP and PIV here.