A look at how defense contractors and the US Air Force are increasing verification confidence and deploying digital twins.
Watching the aerospace and defense verticals, one of the most impactful publications in 2020 was probably Will Roper’s “There Is No Spoon: The New Digital Acquisition Reality.” Using visuals from “The Matrix”, which at the time was called “the first movie of the 21st century,” the Assistant Secretary of the Air Force for Acquisition, Technology, and Logistics painted a picture of a “simulation first” development process. Roper considered the implications of learning things in virtual environments and transferring these learnings to the real world profound. Roper’s keynote, a blueprint for “Disruptive Agility for a Disruptive World,” at the Air Force Association’s virtual Air, Space & Cyber Conference focused on development cost and avoiding respins. He referenced examples from the commercial world to motivate the need for agility.
Several vital trends drive the aerospace and defense domain, including offshoring aspects and a growing number of cyberattacks requiring new safety and security levels. The ever-changing political climate and a new guard of engineers has changed the personnel involved. Furthermore, obsolescence and trust drive the need for modernization in the US Department of Defense (DoD) and across the globe. Microelectronics is a crucial part of it all.
Digitalization in aerospace & defense applications.
Some of the largest aerospace and defense companies presented various related aspects last year, focusing on the key themes of safety, security, and digital twins.
To increase verification confidence for today’s ASIC and FPGA designs, BAE illustrated how they applied automated simulation execution and regression triage with verification planning tools and automated interconnect test development on the development of the RAD510 Space Processor. Bringing hardware and software together, BAE, Dover, and Cadence showed real-time cybersecurity protection for an aerospace and defense system, preventing the exploitation of software vulnerabilities by immunizing processors against entire classes of network-based cyberattacks. Every instruction executed is monitored to ensure compliance with a defined set of security, safety, and privacy rules. Immediate alerts are issued in case of a violation, enabling the system to take a defensive response in real time. In one example of a cyberattacked drone, the answer could be to activate an alternate, “safe” application where the device would stop listening to the network and pull an encrypted GPS location from memory.
In a digital twin case study, Northrop Grumman Corporation (NGC) presented a complete system-on-chip (SoC) digital twin in an emulation environment to execute bare metal and OS-level software tests on the hardware description prior to tapeout. They were able to test processor coherency and Level 3 cache data handling for one of NGC’s multicore SoCs. The use of digital twins to speed deployment of defense systems has been a subject of discussion since it was articulated by Dr. Michael Grieves in 2002. DoD contractors are forced to look at more efficient verification methods before taping out an ASIC so as to decrease risk and increase the confidence of first-time-correct silicon.
With demand for higher system integration levels, novel heterogeneous packaging technologies are emerging in the aerospace and defense vertical as a viable path toward increased input/output (I/O) density and improved system performance. These non-standard processes provide greater flexibility in terms of system design and capability. However, they require new design flows for system-level planning, modeling, and verification—just as outlined in Will Roper’s “simulation first” blueprint.
Power modeling and timing analysis are critical in guaranteeing reliable system performance. The Air Force Research Lab (AFRL) illustrated flows to compose an atypical design process, giving improved visibility and control across integrated circuit (IC), package, and board efforts to enable these packaging solutions. AFRL created a compelling, cross-domain simulation and verification environment executed by a small and agile design team.
These examples show how, when working together in an increasingly complex supply chain, trust between the various partners has never been more critical. The Defense Microelectronics Activity (DMEA) accredits suppliers in integrated circuit design, aggregation, broker, mask manufacturing, foundry, post-processing, packaging/assembly, and test services to ensure that trust. These services cover a broad range of technologies and are intended to support both new and legacy applications, both classified and unclassified. Additionally, the trusted suppliers’ trusted flows are adequate to protect critical program information. And conversely, the DoD requires services to be procured from an authorized supplier accredited by the DMEA on this list.
It’s a brave, digitally transformed future in aerospace and defense, too!
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