Do We Have Enough Standards For An Open-Chiplet Ecosystem?

For some time now, the semiconductor industry has been discussing the development of an open chiplet ecosystem. The idea is that, rather than having monolithic systems on a chip, it should be possible to combine smaller, specialized chiplets in a modular way – ideally across different manufacturers. Doing so would promise great flexibility with much shorter development times, resulting in much better reusability. This is particularly important in applications beyond the realm of data centers: automotive, military, aviation, and measuring device companies, in particular, are looking at such developments and want to take advantage of them.

Despite these advantages, little in the way of such modular systems has yet been seen in practice. Although major players such as NVIDIA, AMD, and Intel have pushed ahead with their own chiplet approaches, a cross-manufacturer standard is largely lacking. This is a result of technical challenges, such as interoperability, standardized interfaces (e.g., UCIe), thermal design, and packaging processes, as well as of economic interests and proprietary strategies.

However, the issue of standards is essential for a functioning chiplet ecosystem.

Standards for die-to-die interfaces are currently the subject of intense debate in the semiconductor industry. There are now several competing approaches – Universal Chiplet Interconnect Express (UCIe), Bunch of Wires (BOW), and Advanced Interface Bus (AIB) – each designed to enable communication between individual dies within a chiplet system. However, these standards focus exclusively on pure die-to-die data traffic.

But a full-fledged chiplet ecosystem requires much more than just standardized data connections. Practical implementation of such a system calls for further technical parameters and exchange formats – particularly in the area of energy supply. For example, the power/ground network in the interposer, i.e., in the connection layer between the chiplets, must be designed with precision. That makes it necessary to know the power consumption of each individual die in advance. In addition, the target impedance plays a central role in ensuring signal and power supply reliability. Without defined standards for this information, designing the power supply structure remains a complex, individual, and costly undertaking.

Another problem arises from the scaling of physical structures: while the rules that applied in classic printed circuit board (PCB) design were comparatively simple, these quickly reach their limits in interposer design. The cable spacing and widths are significantly smaller in the interposer, which means that the power – especially at high currents – comes very close to the physical and technological limits. This requires much more precise planning and simulation, for which there are hardly any standardized data exchange formats at present.

A modern chiplet system usually integrates numerous different interface protocols – including PCIe, USB, MIPI, SerDes links, and other specialized high-speed interfaces. This diversity is necessary in order to efficiently connect different functional blocks with each other and to enable external communication. But it is precisely this heterogeneity that presents interposer designers with major challenges.

Each of these interfaces has specific requirements for the physical layout of the interposer, such as impedance specifications, length matching, crosstalk thresholds, and distances to other signals. These design rules are documented in the corresponding specifications of the interface standards. However, these standards are developed and published by different organizations, among them PCI-SIG, USB-IF, MIPI Alliance, and JEDEC – each with their own documentation formats, levels of detail, and access conditions.

In practice, this means that the interposer designer must have access to all relevant specifications, analyze them carefully, interpret them, and implement them correctly. Not only does this call for in-depth technical understanding, it also takes a considerable amount of time and coordination. A uniform overview is often lacking, and it is not uncommon for standards to have conflicting requirements. In addition, many of the documents are accessible only after paying for license fees or memberships, which further complicates the development process.

An overarching, uniform metastandard – as part of an open chiplet ecosystem, for example – could do much to increase efficiency here. Such a standard wouldn’t necessarily have to replace the existing protocols, but rather make their relevant physical parameters available in a consolidated form. Ideally, this information would be machine-readable and could be integrated directly into the EDA toolchains, enabling automated rule checks and constraint management.

Similar problems also occur when simulating the transmission behavior. The modeling data required for this is often available in different formats and documents, which makes consistent integration into simulation tools difficult. A certain degree of standardization is achieved through IBIS models, which describe the electrical properties of I/Os across manufacturers. There is scope to build on this in the future – but IBIS models alone may not be sufficient for complex chiplet systems. Further standards are needed to ensure interoperability and efficient simulation. Problems similar to those in design and simulation also occur during commissioning and troubleshooting. There are currently no uniform formats or standardized data models that would simplify analysis and diagnosis in the event of a fault. This makes each commissioning very individual and dependent on the developer’s experience – especially when integrating several chiplets from different origins.

Structured electronic models that map typical fault modes or provide diagnostic data would be extremely helpful, especially in the event of a fault. In the event of a communication failure, for example, such models could suggest possible causes – such as timing problems, impedance deviations, or voltage instabilities – and thus greatly speed up troubleshooting.

One central problem is that the commissioning engineer often lacks the necessary knowledge of the internal structures of the interfaces used. Without insight into the protocol logic, internal statuses, or specific implementation details, targeted diagnosis is hardly possible. Here, too, a comprehensive standard that defines and makes accessible diagnostic data, internal status information, and protocol descriptions could play a decisive role – not least in reducing development time and support costs.