Dynamic CDC Jitter For Clock Domain Crossing (CDC) Signoff

By Himanshu Bhatt and Paras Mal Jain

Detecting and debugging deep sequential CDC convergences using structural CDC verification is extremely difficult since doing a flat analysis on large designs has capacity related challenges, and even if verification tools can complete the analysis, it becomes a nightmare to debug the violations with complex sequential logic. Thus arises the need for dynamic CDC verification using metastability injection (CDC jitter) mechanism during simulation. Traditionally designers use RTL macros to model CDC jitter which faces multiple challenges as listed below:

• False injection which may arise due to either the data changing synchronously or data not changing closer to the clock edge
• No coverage to qualify the robustness of the test vectors used for jitter injection
• No debug capabilities
• Increased simulation run-time with CDC jitter macros

Therefore, an advanced and native CDC jitter approach is needed to overcome abovementioned limitations. This blog describes a solution that aims to provide a very powerful debug and coverage mechanisms using the best of both static and simulation.

Metastability problem

Metastability

In the figure above, there is a path between clocks C1 and C2 and both these clocks are asynchronous to each other. Clock C2 edge can come anytime with respect to C1 since there is no defined relationship between these clocks. When output S changes very close to C2 transition violating the setup/hold time, it will cause metastability, thereby causing the output M to be indeterministic. This metastability can cause chip failure. Chip designers add synchronizers eliminate the effect of the metastability. When such multiple synchronizers converge in the downstream logic, it can cause data coherency due to cycle uncertainty. Let us understand it in more details in the below section.

Challenges of Structural Convergence Checking
In the below example, assume that D1 and D2 are two source signals which synchronize in the same clock domain to avoid metastability. But still there is cycle uncertainty, due to which Sync1 and Sync2 may settle to different values for one cycle.

Let us assume S1 and S2 both have transition from 0 è 1. However, due to cycle uncertainty, Sync1 received the old value (0) and Sync2 received the new value (1). The expected transition was 00 è 11, however the actual transition becomes 00 è 01. Assume that the downstream logic which handles these transitions is a state machine. It may know how to handle a “00” or “11” transition but may not know how to handle a “01” transition so it would deem this transition as illegal. This would lead to a functional failure in the design.

Convergence, another challenging CDC problem

Structural CDC verification becomes inadequate for deep sequential convergences in the design due to performance and debug challenges. Designers use a variety of solutions to overcome these convergence verification challenges. Traditionally they use RTL macros that inject random delays on CDC paths to mimic metastability. Based on these injected delays, test vectors are run and functional failures (if any) during these test runs are analyzed.

The challenges with these traditional jitter solutions are that the delay injection may not be accurate. The data during delay injection can change synchronously or data may not change close to clock edge. Debugging any test failures due to these delay injections is quite tedious. Also, there is no data to qualify the robustness of the test vectors.

Dynamic CDC jitter verification
A dynamic CDC jitter verification solution generates better control signal jitter injection models for CDC convergences. Below is the Synopsys flow for dynamic CDC jitter verification:

Synopsys Dynamic CDC Jitter Verification

This flow uses CDC jitter analysis using static verification and simulation. The static tool generates the database which essentially contains the metastability models inserted for CDC jitter analysis. This jitter database is then used by simulation through native integration with minimal changes needed in the simulation setup.

Following are the advantages using this flow:

Summary
Traditional CDC jitter solutions lack accuracy and are tedious to debug. Synopsys offers dynamic CDC jitter verification, which provides improved Verdi debug, coverage with enhanced reporting, with less noise and easy integration between VC SpyGlass static and VCS simulation tools. To learn more about Synopsys CDC jitter, register for the webinar here.

Paras Mal Jain is R&D Director for CDC and SDC Constraint products at Synopsys. He has been leading CDC products for 15 years. He has a bachelor’s degree in Computer Science from BITS, Pilani (India) and based in Mountain View.