Easier Assertion Development And Debug With Simulation Replay

By Vin Liao and Robert Ruiz

Assertions and assertion IP (AIP) are a core part of the register transfer level (RTL) verification environment for all modern chip development projects. Assertions can be considered as statements of design intent, specifying how the design should behave—and not behave—under specified conditions. They range from simple statements, for example, that a multi-bit signal should always be one-hot, to complex AIP checkers for bus protocols or execution rules for instructions in processor pipelines.

The value of assertions

The assertions in virtually all contemporary projects are expressed as SystemVerilog Assertions (SVA). This subset of the widely used SystemVerilog design and verification language serves two primary purposes in chip verification. SVA is commonly used within the design and alongside the Universal Verification Methodology (UVM) testbench to check for proper behavior and flag any violations of intent during simulation. Assertions are entirely complementary to the UVM components, especially since testbenches tend to focus on the I/O while SVA checks internal operation.

The other primary use is during formal verification, when SVA both defines intended behavior and establishes the environmental constraints on design inputs. In such a case, it is considered important to include the assertions in all testbench simulations. This helps ensure that the assertions are correct and that the constraints are not set too tightly. Otherwise, if formal analysis fails to consider legal input combinations or sequences, it will not analyze the full range of intended design behavior and is likely to miss bugs.

Assertions enable design engineers to monitor the behavior of a design during all phases of verification. They ensure that the design aligns with a specific protocol or set of values, thereby reducing the risk of undetected errors that could compromise the final product’s functionality. The critical role of assertions in identifying and rectifying bugs early in the design cycle underscores the importance of developing them quickly and without errors.

Traditional assertion development and debugging challenges

Historically, the process of developing and debugging assertions has been a complex and time-consuming endeavor. Engineers are required to compile the design, the testbench, and the assertions, and then run the simulation for each individual test. Just as with any type of code, engineers make mistakes when specifying SVA, especially during the early part of the process. Any issues that arise with the assertions require modifications, which are then followed by a comprehensive recompilation, rerun of the simulation, and generation of an FSDB trace (signal waveform) file for debugging.

This traditional process can become particularly lengthy and cumbersome when the design and testbench are large. Each iteration can take several hours, or even a few days. The need to repeatedly involve the design and the testbench to generate an FSDB for every assertion change adds to the complexity and length of the process. This issue highlights the need for a more efficient and streamlined approach. Fortunately, assertion debug is one of several simulation challenges that can be made much faster and easier with new, automated simulation replay technology.

Simulation replay to the rescue

The whole point of simulation replay is to make each iteration of the compile-run-debug loop much shorter. The entire design undergoing verification is replaced by an automatically generated testbench stub that replays full-design simulation activity. Removing the design from many simulations yields much faster performance and a much shorter turnaround time (TAT) when debugging assertions. Since SVA code can be quite complex, especially with AIP, multiple loops to fix and verify each issue are usually required. This makes short TAT even more important.

Simulation replay has been shown to be effective at accelerating assertion development and debug. Users routinely report that this approach saves them hours to days of time for each SVA issue discovered. In addition, replay simplifies the process with fewer, smaller files for the simulation and design data. This encourages the use of assertions as part of the verification process, improving error detection during simulation and enabling formal verification.

Synopsys VC Replay provides all the simulation replay capabilities and features needed to make assertions easier to develop and debug. As noted earlier, there are several other simulation challenges that are addressed by simulation replay:

• Debugging a UVM testbench and its checkers – as with assertion debug, the entire design is replaced automatically by a stub, resulting in faster simulation performance and shorter TAT
• Sub-design simulation – Synopsys VC Replay automatically captures the simulation activity around a sub-design in an FSDB file, creates a new sub-design testbench, and runs a standalone simulation
• IP simulation – sub-design simulation allows an IP provider to run with an IP-only FSDB so they do not require any proprietary information from the full design or testbench
• Early, accurate power estimation – Synopsys VC Replay runs gate-level simulation (GLS) on the netlist using RTL simulation results with an automatically generated testbench
• Faster GLS of automatic test pattern generation (ATPG) patterns – replays load in the state values from the end of the common initialization sequence so that only differentiated vectors are simulated

Summary

Assertions are a key part of modern chip verification, but developing and debugging can suffer from a long TAT. Simulation replay speeds up the process significantly for assertions as well as for power analysis and other important simulation tasks. Synopsys VC Replay users have found that the faster, smaller simulations run 10X-100X faster than full-chip, full-testbench simulation. This saves project resources and shortens time to market (TAT), a desirable outcome for every project team.

Robert Ruiz is the director of product management at Synopsys, Inc. Ruiz has held various marketing and technical positions for the test automation and functional verification products at Synopsys, Novas Software and Viewlogic Systems. His background includes over 17 years in advanced design‐for‐test methodologies as well as several years as an ASIC designer. Ruiz has a BSEE from Stanford University.