Different Economies Of Scale, And Lots Of Questions

The industry appears poised to adopt a number of different approaches, but what does that really mean?


Being able to shrink features and reach the next node is already an exclusive club. It will become more exclusive at 16/14nm, which is expected to hit volume production in 2015, and even more exclusive still at 10nm. In fact, it may begin to look like a semi-private affair.

The argument being presented is that economies of scale will still exist for those companies with pockets deep enough to build and manufacture these chips. But the entire semiconductor manufacturing industry is about to undergo some significant changes that could leave many in a the kind of head-shaking denial that former AMD CEO Jerry Sanders made famous in 1994 when he insisted the foundry model wouldn’t work and that “real mean have fabs.”

The reality is that no one has digital fabs anymore—at least not exclusively. Even Intel and IBM can’t afford to go it alone. Just developing advanced processes and designing chips for those processes is incredibly complicated. Almost counterintuitively, though, it still can be highly profitable for those companies that can afford the price of admission, providing everything works as planned and demand and volume remain consistent or up.

That’s a big “if” of course. Providing all the pieces fall into place, fewer companies might be able to churn out highly sophisticated SoCs using less upfront investment by foundries. The rationale is that there will be nearly as many chips overall but with a much more limited number of design options. That allows processes to be optimized, manufacturing and assembly to be streamlined, and ultimately less equipment even though each individual piece of equipment may be more expensive.

One alternative is stacked die, which can tie together more disparate designs regardless of process technology. On paper, this approach looks quite attractive, as well, particularly for 2.5D. In fact, given the potential bandwidth and power/performance improvements, it could forestall Moore’s Law for digital logic for a couple years, at which point either lithography options will be clear or 3D-ICs will become more attractive. And there is an option of staying at 28nm in the interim, swapping to new substrate materials and perhaps even adding some architectural and packaging changes to improve throughput and reduce power even further.

All of these are viable options. That’s both good and bad. The good news is that area, power and performance all have plenty of room for improvement. The bad news is that a splintered industry doesn’t have the kind of collective intellectual clout to solve really tough engineering issues that made it one of the most concentrated centers for innovation in history. And even worse, concentrating that kind of potential into the hands of a few companies will only stifle it—maybe not in a year or two, but certainly over time.

Economies of scale are more than just an accounting exercise when it comes to technology. They’re a combination of good business practices coupled with a sustained investment in new ideas and unusual approaches to problem solving. Unfortunately, it’s the latter that usually gets cut first even though it’s really the engine that drives the business. Maintaining both will require an industry that marches forward in sync—even after Moore’s Law is no longer providing the drumbeat.

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