Evaluate ESD protection for interconnect robustness to ensure adequate handling of an event.
Protection against electrostatic discharge (ESD) events is an extremely important aspect of integrated circuit (IC) design and verification, particularly for 2.5/3D designs targeted for automotive systems. ESD events cause severe damage to ICs due to a sudden and unexpected flow of electrical current between two electrically charged objects. This current may be caused by contact, an electrical short, or dielectric breakdown.
No matter the cause, all ESD events can cause a metal melt, junction breakdown, or oxide failure. ESD can damage an electronic component at any stage of its production or real world use if not properly prevented. ESD events can cause ICs to fail prematurely, or to operate at less than designed functionality, neither of which is good for market reputation.
2.5D/3D ICs have evolved to enable innovative solutions for many design and integration challenges. As shown in figure 1, 2.5D ICs often have multiple dies placed side-by-side on a passive silicon interposer. The interposer is placed on a ball grid array (BGA) organic substrate. Micro-bumps attach each die to the interposer, and flip-chip (C4) bumps attach the interposer to the BGA substrate. In 3D ICs, dies are mounted on top of each other. Connections made between stacked dies and the substrate implemented using through-silicon vias (TSVs).
Fig. 1: 2.5D versus 3D IC designs.
3D ICs are attractive for safety-critical devices like automotive sensors, advanced driver-assistance systems (ADAS) and autonomous vehicles (AVs). 3D ICs are compact, high-performance chips that can process vast amounts of data in real time. in these devices is a top priority to ensure that they function For these applications, where safety and reliability are extremely important, ESD robustness helps ensure that the electronic systems function reliably under various operating conditions.
Multiple protection schemes are in use today, and others have been proposed to avoid or mitigate ESD damage [1,2]. IC designers are required to add proper ESD protection schemes to their chips. These schemes are added in the schematic to facilitate early checking, and in the layout, to ensure correct physical implementation. Of course, checking these ESD protection circuits to ensure they are adequate and properly implemented before fabrication is an essential part of design reliability verification [3,4]. ESD protection design rules are included in design rule manuals to enable designers to verify the presence of appropriate ESD protection from a topological perspective.
Verification of adequate ESD robustness requires evaluating ESD protection for proper construction and interconnect robustness to ensure adequate handling of an ESD event. Two areas are evaluated for interconnect robustness: point-to-point (P2P) parasitic resistance and current density (CD).
Measuring P2P resistance requires calculating the interconnect resistance between a given external pad (or cell port) and the corresponding ESD device pin and reporting the total resistance. Measuring CD requires calculating the current density in every polygon on every metal/via layer from a starting pin (or port) to an end pin (or port) by injecting an appropriate current at an external pad and measuring CD on all interconnect polygons up to the ESD device pin.
Automating ESD verification in 2.5D/3D ICs introduces additional challenges that we don’t see in 2D “traditional single die” ICs. Industry white papers [5] and IEEE publications [6,7] have outlined and provided extensive background material for many of these challenges, like differentiation between IO types, corresponding HBM/CDM constraints, working with a mix of different technology nodes and foundries, and taking care of different ESD methodologies. These challenges are summarized in figure 2.
Fig. 2: Challenges for automating ESD verification in 2.5D and 3D ICs.
A systematic methodology can be formulated to address the ESD challenges and verify the ESD robustness of 2.5D and 3D ICs using an automated process. This methodology provides interconnect ESD P2P/CD verification. It starts by performing die/interposer ESD verification, followed by assembly analysis using a 3D IC physical verification tool. This results in obtaining system-level interconnect P2P/CD results.
Inputs for this verification methodology should be:
Outputs should be:
At Siemens, we’ve implemented this methodology using Calibre 3DPERC (die2die) as demonstrated in figure 3 and figure 4.
Fig. 3: Interconnect ESD P2P/CD verification methodology (using Calibre 3DPERC (die2die)).
Fig. 4: Inputs/outputs of Calibre 3DPERC (die2die).
Hybrid bond technology [8] makes millions of connections in a square millimeter of silicon. With the hybrid bond technology, the number of bumps has increased dramatically, and the designers want to perform P2P/CD measurements based on each bump. This leads to an exponential increase in the number of pin-pairs to be processed. Additionally, the total amount of simulations increases dramatically with this approach. Therefore, the ESD verification tool should prepare the die/interposer P2P/CD measurements to be 3D-aware while performing the 2D runs (which can be done by Calibre 3DPERC).
ESD protection is an essential element in IC designs, particularly for safety-critical automotive applications, where 3D ICs are becoming more popular. While automated verification of the accuracy and capacity of an ESD protection circuit is an established process for 2D IC layouts, 2.5D/3D IC design ESD protection verification must overcome additional challenges that, until now, have resisted automation.
A new automated ESD verification methodology effectively and accurately addresses the emerging challenges for ESD robustness in 2.5/3D IC designs, and is available in Calibre 3DPERC (die2die). Moreover, it also supports hybrid bond technology with 3D-aware die analysis. Ensuring accurate and consistent ESD protection in 2.5/3D ICs raises the reliability and product life of ICs used for automotive systems, ensuring they deliver the value and functionality the market demands.
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