A technical paper titled “A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers” was published by researchers at Università degli Studi di Catania, Italy.
Abstract
“This paper presents an efficient solution to reduce the power consumption of the popular linear feedback shift register by exploiting the gated clock approach. The power reduction with respect to other gated clock schemes is obtained by an efficient implementation of the logic gates and properly reducing the number of XOR gates in the feedback network. Transistor level simulations are performed by using standard cells in a 28-nm FD-SOI CMOS technology and a 300-MHz clock. Simulation results show a power reduction with respect to traditional implementations, which reaches values higher than 30%.”
Find the technical paper here. Published September 2022.
G. Giustolisi, R. Mita, G. Palumbo and G. Scotti, “A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers,” in IEEE Access, vol. 10, pp. 99702-99708, 2022, doi: 10.1109/ACCESS.2022.3207151.
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