Integrate dies, and co-optimize thermal and power integrity to ensure design feasibility and accurate signoff for system-level effect.
Many industry trends are driving chip developers to consider multi-die designs using advanced 2.5D and 3D technologies. Such designs enable incorporating heterogeneous and homogeneous dies in a single package, increasing density while reducing signal propagation times. However, multi-die designs introduce new challenges that must be addressed by all relevant electronic design automation (EDA) and IP products in the development flow. Perhaps the biggest impact is on the implementation tools that transform the register transfer level (RTL) design into layouts suitable for manufacturing.
This white paper explains how Synopsys UCIe IP and 3DIC Compiler are integrated to deliver a pre-verified and pre-tested design reference flow with all the required design deliverables such as automated routing flow, interposer studies, and signal integrity analysis. The combination of the products helps designers efficiently integrate dies, and co-optimize thermal and power integrity to ensure design feasibility and accurate signoff for system-level effects.
Read more here.
Fig.1: UCIe on interposer view in Synopsys 3DIC Compiler.
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