Executive Viewpoint: Qualcomm On Process Technology

Semiconductor Engineering sat down to discuss current and future process technology challenges with Geoffrey Yeap, vice president of technology at Qualcomm.

SE: You have pointed out there is a fundamental shift taking place at the 28nm logic node. This is the first node in which mobile chips have been ramped up first within the foundries, ahead of computing-based ICs. Many believe that 28nm will be a long running node. Do you agree?

Yeap: Yes. Just look at the cost. A very good example is 28LP technology, yielding the lowest die price due to its low process/bump cost. At 28nm, you have at least two or three flavors. You have POLY/SiON, which can supposedly enable devices up to 1.9-GHz. Let’s say the low-cost mobile SoC market three years from now needs to be more than 2-GHz. POLY/SiON may be able to handle that. Then, you have HPM (high-performance mobile) process technology. HPM may be the next mainstream technology at the 28nm node, depending on the cut-off of the CPU frequency requirement.

SE: Have you made the transition from polysilicon to high-k/metal-gate at 28nm?

Yeap: Absolutely. Right now, high-k is actually at the high-end. Take (Samsung’s) Galaxy Note 3. That’s the one that goes with Samsung’s Galaxy Gear watch. The Galaxy Note 3 is using a high-k/metal-gate device operating at 2.3-GHz. We also just announced the Snapdragon 805. That’s also based on 28nm high-k/metal-gate. That one will go up to 2.5-GHz with even better graphics.

SE: The 20nm planar node has taken some criticism. It’s unclear if 20nm planar technology maintains the traditional cost-per-transistor reduction curve. What about 20nm?

Yeap: We have already announced a product. This is a fourth-generation LTE modem based on 20nm. With 20nm, there is still a die-cost reduction. It may not happen as quickly as in some of the better nodes like 65nm or 28nm LP. But 20nm will have a cost crossover. We think we will ramp up this product in 2014.

SE: As you know, the foundries are developing finFETs. The initial finFETs at the foundries are based on a 14nm-class fin technology with a 20nm backend. How would you compare 20nm planar and 16nm/14nm finFET technology at the foundries?

Yeap: FinFET is great in terms of performance and power. The cost increases only marginally, perhaps to the low single digit. But if you look at 20nm as well as the 16nm finFET or 14nm finFET, it’s actually the same node. It’s just a transistor change. You can think about it as simple as that.

SE: When does Qualcomm plan to move to finFETs?

Yeap: We are moving there. We already have a 20nm modem. So, you can easily guess when the finFET will come. One node generation is two years. But 20nm planar to 16nm finFET is not an actual node generation. The backend does not change. It’s just a transistor change. So it won’t take two years to introduce finFETs. It will take much less time than that.

SE: Intel is developing its second-generation finFET technology at 14nm. Unlike the foundries, Intel’s 14nm finFET technology will have a 14nm backend. Does that give Intel an advantage in terms of area scaling?

Yeap: Intel showed that their wafer costs are increasing. But at 14nm, they are claiming that they can do more area scaling than what they have achieved before—substantially more. So basically, even though wafer costs are going up faster, they claim that they can scale to smaller dimensions even faster. So that is very interesting.

SE: Did the foundries take the right approach by developing their first finFETs based on a 14nm-class fin with a 20nm backend?

Yeap: We have to admit that Intel, of course, knows finFETs. They are the leader. But given the constraints of the other guys, it’s a big risk to move to everything new, including the backend and interconnect. Given that constraint, it’s a smart move to do it this way. But the only downside is when you go to finFET, you only have a very minimum die reduction. This isn’t a technology node where you can get 40% or 50% die reduction. On the other hand, finFET transistors provide better performance. So we can translate some of the performance into a small area gain or reduction. It’s maybe 5%. So you have a die reduction, but it’s pretty small compared to an actual technology node.

SE: On the other hand, the foundries took less risk in their initial finFET efforts. Is that right?

Yeap: Yes. Backend is where you are doing the interconnects. That’s where you get the die shrink. So you need that in order to get an area shrink. But you have to pay a lot to get that. That’s why there is a lot of interesting data you need to look at. You have to look at the tradeoffs. Is it better not to shrink that much and then the cost will not increase that fast? A lot of work needs to go into that. So, the finFET migration is actually similar to our ramp at 28nm. The 28LP process, which is POLY/SiON, ramped first at the foundries. Later on, we had the 28HPM, which is a high-k/metal-gate process for mobile. So, you start at one point and then move up. In other words, we moved from a polysion to high-k. The backend is the same.

SE: Are you satisfied with the progress with finFETs at the foundries?

Yeap: Yes. There is already a guy working on the second-generation finFET. If you are currently working on the first-generation, that means you are one generation behind. So you want to close the gap. But the foundries are closing the gap.

SE: Is TSMC your initial finFET partner? Are you going to work with one or all of the foundries in finFETs?

Yeap: I can’t comment on that. TSMC is the largest foundry. Of course, Samsung and other people are developing finFETs.

SE: Intel has recently announced plans to expand its foundry business. Would Qualcomm entertain the idea of using Intel’s foundry business?

Yeap: I listened to Intel’s recent analysts meeting. Intel’s CEO has a good attitude. He said he wouldn’t close the door on anybody. So he wants to talk to everybody. My answer would be similar. If people are willing, then, of course, we would like to check it out, look it over and compare. But as you know, technology is one thing. The foundry business consists of technology, manufacturing and capacity. You cannot have a table with just one leg. You need more. And, of course, there is price.

SE: In the foundry business, Intel has mainly garnered customers in the FPGA business. That’s different than running a high-volume foundry business, right?

Yeap: You are completely correct. The FPGA companies run a thousand wafers per quarter or something like that. A guy like us, Broadcom or Nvidia runs thousands upon thousands of wafers per quarter.

SE: For years, Intel has been trying to crack the cellphone chip business. They compete with Qualcomm and others. But it’s still unclear if Intel will ever succeed in the mobile space, right?

Yeap: They come from the PC market. They have bleeding-edge performance, but they chew up a lot of power. From there, they are taking steps down. They are more focused on tablets right now, rather than just the smartphone. They appear to be taking steps from the desktop, to laptop, to the low-power laptop, to the tablet and then the smartphone. In the past, they have tried to jump several product levels down, but that’s never been very successful.

SE: Getting back to process technology, you have mentioned that the backend-of-the-line (BEOL) is a major challenge for the industry, right?

Yeap: It’s a big challenge. If you think about the increased costs, it all starts at the backend. By backend, I mean the interconnect. For example, there is a drastic cost increase for 20nm. That’s because you have a new module called the middle-of-the-line of local interconnect. That darn thing in 20nm costs five masks. If you project that to 10nm, that number can easily double. Every mask uses the most advanced litho tool, which is immersion. So the backend is partially driven by litho, resists, materials and the whole the nine yards.

SE: Regarding lithography, extreme ultraviolet (EUV) and other options are late. Can you continue to extend 193nm immersion for the foreseeable future?

Yeap: First of all, you have no choice. There is also a multiple patterning approach called self-align double patterning. That approach looks very good. The NAND guys already use that. There is an inherent know-how in doing it. Of course, in logic, we need to customize that for our needs. So for further scaling, everybody is counting on that.

SE: Any thoughts about 2.5D/3D stacked die?

Yeap: This is a personal opinion. There is a lot of wisdom to be learned and how the semiconductor industry works. Look at flip-chip. When did it get invented? When did it get used first? And what about this technology in the mobile space? It took a long time. IBM invented it in the 1960s. They started using it in the 1970s, maybe the 1980s. A lot of those types of technologies will be used by products or markets that can afford it. For mobile, our figure of merit is always cost, PPA and design. You think about 3D TSV. It’s just connecting things and doesn’t make transistors smaller. The only thing that 3D TSV can do is to reduce the power, which is very important. But if you are looking at area shrink, 3D TSV itself does not do that. It still has high costs. So, there are other and better solutions. I don’t know if it’s 2.5D or a lower-cost interposer option. Or maybe it’s a fan-out WLP. Those things are inherently less expensive relative to 3D TSV.

SE: What about technologies beyond silicon-based finFETs? Any thoughts?

Yeap: We monitor it. We recently joined Sematech and Imec. From there, we understand the progress of various technologies. FinFETs can scale to the 10nm node. But after that, we need something else. Maybe III-V finFETs. But III-V mixed with silicon is hard to do without having defects. At the recent IEDM, one session talked about graphene. The speaker was very clear. He said graphene can do certain things. As a replacement for silicon technology, he said no. But it’s still very early to tell.