Reset design challenges and effective verification techniques using static technology.
It is difficult to imagine an aspect of semiconductor development more fundamental than reset. The ability to initialize the entire hardware design and clean all software running through a system-on-chip (SoC) is essential. Stating with a known state avoids propagation of signals with unknown values. Despite the best efforts at verification, lingering corner case bugs may put a system into a state where reset is the only solution to flush unknown values. Transient faults such as particle hits, cross talk and environmental effects can also create a situation where reset is required. Low-power design techniques that rely on turning parts of the design on and off require the ability to reset. For these reasons and more, the number of reset domains in SoCs has been growing and will continue to increase.
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