Experts At The Table: Designing At 28nm And Beyond

First of three parts: Stacked die; the impact of software and integration; the changing role of EDA; who will be left standing and what they will make.


By Ed Sperling
System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz, Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), and Charlie Cheng, CEO of Kilopass.

SLD: As we move to 28nm and below, what will we have to do differently than in the past?
Sherwani: We see issues at the system level. One involves 3D chips (stacked die). How do you actually put these together? Memory already has gone 3D. Electrical, physical and mechanical tools, both on the simulation and analysis sides, are not that sophisticated. Most of that work is being done manually today. Second, we have several customers that have come to us and asked us to put two or three chips together at 22nm. The science to combine the chips is not well known. This exercise is costing more than if it had been done from scratch. You should be able to do this very quickly. We don’t have tools like that, so we will have to develop them. A third area is that we see our design teams growing, but our verification is growing super-linearly. Right now verification teams are almost 3x the time of other teams. That is not sustainable.
Schirrmeister: Somewhere around 40nm software became more dominant. It passed the effort needed for hardware. How do you create for this vast mass of available space new things to differentiate your chip? And how do you integrate all of these pieces together? The whole integration and verification in the context of the software and the hardware together is the big challenge.

SLD: Does that software include just just the drivers, or is it more?
Schirrmeister: It goes all the way up to the application level. The more enabling hardware you have, the higher up to the software you reach because you need to partition which component runs, which processor it uses. There are different layers from the very low-level bare metal to applications that may be split across different processors.

SLD: Let’s go back to the original question. What challenges are ahead?
Janac: One of the things we’re trying to do is to bring computing closer to the person. It’s going from the mainframe to PC to smartphone, which will be the new personal computer. What people are trying to do is build things of frightening complexity into something as small as a smartphone and with the functionality of a PC. They’re not quite there yet, but they’ll get there. At 28nm, we’ve got power domains, frequency domains, disparate pieces of IP on disparate chips, and we’re trying to re-use software. You have to make all of that work together. That’s one of the biggest challenges. You have IP with different protocols and sources. There are requirements that looked like science fiction a few years ago. And you have to make it all work. It’s a very big challenge and it’s very costly. Some of these things cost hundreds of millions of dollars to build.
Cheng: Integration of software and miniaturization are a challenge we’ve been dealing with over the past three decades. It’s not just 28nm that’s the problem. But what 28nm does bring is very different packaging, which drives the silicon decision, as well as confusion in transistors. That will cost the industry $10 billion to $30 billion. The reason is that 28nm is supposed to be the generation of high k/metal gate. I’m not sure that’s going to happen. TSMC has re-introduced bulk silicon with no metal gates. The question is do you want to take a chance on bulk silicon and save 30% in cost, or go with high k/metal gate that will be more expensive but may not work. That’s a lot of money for an experiment.
Zahiri: Design costs are rising. With 28nm, you’re spending 20% or so more than what we spent in the past. Semiconductors are not growing at that pace. Something has to give. So chipmakers will go in two directions. One is to figure out how to use the same resources and the same schedule and the same number of people to get these 28nm chips out, which are more complex and much bigger. Those that can’t do that will go away. So 28nm, and especially 20nm, will be the test to see which companies will re-tool, re-position and re-architect to take advantage of this real estate. We’re trying to understand which companies will survive and how we can help them.

SLD: We’re talking about complexity and convergence, as well as business issues. As they become more entangled, do we have to rethink everything?
Schirrmeister: According to IBS, at 28nm the price of fab construction is $3 billion; process R&D is $1.2 billion R&D; the design cost is $50 million to $90 million and each mask set is $2 million to $3 million. For 22nm/20nm, fab construction is $4 billion to $7 billion; process R&D is $2.1 billion to $3 billion; design cost is $120 million to $500 million, and a mask set costs $5 million to $8 million. As an EDA vendor, our investment is huge, as well. What you will see, more and more, is the whole notion of collaborative design. It’s hard to do it all by yourself. The business dynamic behind this is becoming very interesting for who can afford to do a design.

SLD: So who can afford to do a design?
Janac: The business models and technology are getting intertwined. There are a bunch of people getting squeezed in a traditional business model, where they have to do more and more to save a lot of money, and their margins are suffering. Their R&D footprints are expanding and they’re trying to fight that with outside IP and more efficient EDA tools. But you also have companies like Apple and Amazon, where they don’t care what the cost of silicon is. They make money in different ways. The silicon is an enabler, and they can afford to make chips that are 50% bigger or to give away their tablets at cost because they have a different business model that supports that silicon effort.

SLD: Can the industry survive on four or five of these large companies?
Janac: One of the key issues will be access to silicon. Where it starts to get problematic is, at some point, even though you have this business model you have to make silicon. So what fabs are able to give you that cost advantage? There are starting to be fewer and fewer of them. As you go to 28nm, you only have a choice of a few players. You have TSMC and GlobalFoundries, plus Samsung and Intel, and then some smaller players on the periphery like ST and Panasonic.
Sherwani: That’s a good point. At 14nm, who are the players going to be? You can basically say it will be four players.

SLD: And what will they be building? Will it be platforms for a stacked die, or just their own chips?
Sherwani: These guys cannot afford to have fabs and make chips just for themselves. That model won’t work. Even Intel is being forced to revisit that model, which is why they’ve got a custom foundry. They’re projecting a need for five to seven years out. Intel is one of the biggest producers of silicon on the planet, and even they are forced to think like that. What will emerge is that people will move more and more toward platforms, with software as a differentiator rather than hardware. So if you look out four years, you may have a home gateway that is a standardized platform with a processor core and I/O chips and some custom silicon, and then a huge software investment that differentiates one platform from another. The hardware differentiation will be less. There will be some custom hardware, but that may only account for 10% or 15% of the hardware. That will be a platform you can get from a few suppliers working with these foundries. That’s how you cut down the costs. You don’t do those kinds of chips. We see a lot of chips, but there isn’t much difference between them. There may be six or seven chips that are essentially the same.
Schirrmeister: If you look at ITRS (International Technology Roadmap for Semiconductors) data, they already have characterized the design challenges in those platforms. There is a networking platform, which is essentially a bunch of packet processing engines with a smart interconnect. There is a stationary platform, which is a compute platform where you have the embarrassingly parallel portion that plugs into a wall outlet. And then there is a mobile platform, where you try to distribute software across different cores. There is a lot of similarity in how the chips are structured at the block level. But there also are a lot of challenges for how IP providers get their design ready for 28nm and beyond, how to integrate all of that. Some of the integration challenges are very complex. And the software on top of that is very difficult to create.

SLD: Where do the tools vendors see their future?
Sherwani: Once the platform is stable, you can always have disruptions. There are very few of those disruptions, though. When Android becomes stable, phones will look very much the same. Then someone will invent a new generation of phones, and until that stabilizes a lot of innovation will happen.
Zahiri: As EDA vendors, we are trying to intercept that innovation. We don’t see the world as just software or hardware. It’s a combination of both. But more important, we see that we are moving this forward. Whether it’s graphics or something that will allow a battery to last two days instead of a day, or whether it’s just making our industry more productive, the consumer market will remain demanding. We are trying to figure out the ways to meet that need and facilitate innovation.

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