Experts At The Table: Next-Generation IP Landscape

By Ann Steffora Mutschler
System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice president of marketing and AEs for IP and systems at Synopsys. What follows are excerpts of that conversation. For part one, click here.

SLD: Getting back to the point about knowing the right approach to take, what are the considerations?
Aitken: In many ways you have to look at what the fundamental constraint is. So if you look at, for example, a mobile phone there’s a fixed power budget and that’s kind of the limiter. The CPU core can draw say, 400 milliwatts of power and that’s it. It’s got this limited power budget and you have to figure out what it can do in that space and you can figure out that essentially the end users want to have more features on their product and therefore the SoC customers are going to want to be able to deliver as much compute power as they can in that space and they want all kinds of clever architectural aspects to it that will let them take advantage of that compute power when they need it. The whole big.LITTLE thing for example, let’s stay within the confines of this budget but at the same time have enough flexibility that we can get when Grandma wants to watch the grandkids on the video that they can see that quickly. There’s a whole understanding your customer, understanding your customer’s customer aspect to it, that’s really key for the IP business. Another chunk that seems to be increasingly important is understanding the different customer space as well from the Qualcomms of the world who really want to just take our architecture license and go with it, to say, some of the Chinese companies that have to get a product out in three months and don’t have time to do anything. They want the best design they can get and they just want it quickly. What’s interesting in those companies is how quickly they are emerging. So you take somebody like Rockchip or HiSilicon or somebody – nobody had heard of them three years ago and now they’re right up there. It’s amazing.
Peterson: Just anticipating what people are going to want and how that gets reflected in changes in standards…For instance, DDR4 is on the upswing right now and by participating very actively in all of these different standards organizations and being really active in the working group, that really helps not only to bring new standards to market but to bring the IP and the verification IP and the other tools that people need to quickly implement and have the competence to implement those standards.

SLD: How do the lower level process activities around IP impact the physical library?
Aitken: From the ARM R&D’s standpoint, by the time a PDK gets to 0.1, it’s, ‘O.K. good, we’re done. Hand that off to production.’

SLD: What about TSMC stating that they now start their development with version 0.05?
Aitken: It means a lot of churn, but it’s really an opportunity for the physical IP vendor to say, ‘Here’s your version 0.05 or 0.01 set of rules that you have. We don’t like one. This one really is a problem, and not only is a problem, but here’s why. If you use this rule then the library is now 20% bigger than if this rule was a nanometer that way.’ And they’ll say, ‘The reason it’s here is because our equipment will not let us produce this new value.’ By actually having that discussion and going back and forth, even though it creates churn, it creates a better product later and we find that we really do have to work at that level with the key foundries and they are doing that with us and with their IP vendors and with the physical IP people at some of these Tier Ones as well. What comes out of that is a huge amount of work and the number of people who can afford to do that is shrinking over time and will continue to shrink. As a result, there’s more and more need for physical IP vendors like ARM or whoever to come in and say, ‘We did the hard stuff and to the extent that it’s possible, we hid it from you.’ That’s a really key thing now because you’ve got things like finFETs. What do they change? How do we keep them from changing too much is what we try to do. We try to keep the challenges that come at the new physical stuff from impacting higher level designers to the greatest extent possible.
Koeter: Just the digital logic rules that make up your standard cell libraries are complicated enough and then you get on top of that all the analog rules which are unfortunately left to later in the process too. That’s one of those things where we often do work with these leading fabs on process qualification (PQ) vehicles and other test structures to nail the analog components well in advance of having production products. In fact, we’ve recently taped out a couple of those PQ vehicles that are pre-0.1 because you need to get the structures; you need to understand the analog performance when you’re dealing with gigahertz+ SERDES – it’s not a trivial task.
Peterson: I also think it comes full circle back to that consumer demand for the newest stuff being ever more quick. I bought this Samsung S3 about three months ago and already I want the S4. What’s chip development time? 12, 18 months? So, you’ve got to start developing at the 0.0x spec in order to be anticipating what people are going to want.
Aitken: And you also have to be putting in some new design capabilities because an aspect of design that has been true for a while and keeps getting more true is that when you move to the next process node, if you are naïve about how you do the design for it, your performance, power, area is actually getting worse. So you actually have to be very careful on architecture, that what you’re doing very carefully for those nodes in order to make going to them justifiable because if you’re the guy who signs checks on a chip, and you say, ‘Why should I pay for 16nm?’ You have to be able to prove that 16nm is better than 20 and that’s better than 28. If you can’t do that, you’re in trouble.

SLD: What is the impact of this on the higher level architecture decisions?
Moll: At the higher level is an interesting development which is dealing with the process and this is extremely complicated but when you have very little time to assemble the chip it means that you just do not have time to even think about it. It used to be that the high level architect would decide that some portion of the clock tree would be custom and things but based on power, it’s entirely gone. Now, maybe a CPU has an implementation package and the SRAMs are the last remaining things that are kind of custom in the middle of the design but assembling the whole thing together is absolutely nothing custom. You just don’t have time to do this. You just entirely rely on EDA tools to do the job for you, otherwise you just don’t have time. And with last minute changes you have to be able to accommodate anything so you don’t have time to have your circuit guys look at any of this stuff.
Peterson: You don’t have time and you may not have the expertise. New standards are coming out so much more quickly than they were even a couple of years ago and every one is way more complex than the one before. So you may literally just not have the expertise on staff or the time to bring that staff up to speed on something and you need to buy that capability.
Koeter: That’s absolutely true. Something as relatively, seemingly and common as USB — the spec of that is about 3,000 pages and there is an enormous amount of configurability in the cores, for example. And yes, there is a standard interface called the PIPE interface, for example, and it sort of defines the data in the clocks – what’s so hard about putting a PHY and a controller together? Standard interface, you plug them together, it should be simple, right? Not so much because when you start talking about integrating that IP, integrating into the test environment, the verification environment, configuring it correctly – this is something where at Synopsys and all of us add a lot of value in terms of helping our customers navigate that path.