Experts At The Table: Stacked Die Reality Check

By Ed Sperling
Semiconductor Manufacturing & Design sat down with Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries; Steve Pateras, product marketing director at Mentor Graphics; Steve Smith, senior director of platform marketing at Synopsys; Thorsten Matthias, business development director at EVGroup; and Manish Ranjan, vice president of marketing for advanced packaging and nanotechnology at Ultratech. What follows are excerpts of that conversation.

SMD: How quickly is stacking happening?
Ranjan: We see a lot of movement toward stacking. Stacking can be defined in a number of ways. There is wire-bond stacking, package-on-package and peripheral stacking. But full 3D stacking with TSVs is going to be a lot more complex to solve with respect to the supply chain. It will take a few nodes to flesh that out. If you take a look at leading-edge microprocessors, it’s common knowledge as to where Intel is with respect to manufacturing—22nm is done, more or less, and they’re going to 14nm next year. TSVs are not in pilot production for 14nm, so it will be sub-14nm. Whether it’s 8nm or 6nm or 3nm or 2nm remains to be seen.

SMD: But Intel is a unique case because its structures are so regular, right?
Ranjan: But you still have the same problems. Cache could be 60% or 70% of the area. You put cache on a separate chip and connect it with a TSV, so you can almost make the argument that from a leading-edge perspective, the problems that Intel sees are what the rest of the industry will see in the next couple years. TSVs are meaningful for them, too.
Matthias: One of the main attractions of 3D or 2.5D is the concept of modularity. Ideally you take some components of your chip and you focus on the memory or CPU or GPU and you do everything else in standard components. If you talk about 22nm and below, even if the manufacturing was free, the design costs are getting so high that very few products can justify the cost. 3D is a way of lowering the cost. A lot of the systems on chip have been developed before. If you find a way to integrate some of that technology and allow each company to focus on their core competencies then you can solve this problem. We are definitely a few years away from making this work, but it’s a really attractive concept. And it will allow you to use 14nm for what you really need it for—the high-speed part of your chip.
Pateras: The heterogeneity of the package is what’s driving it. You’ll see memories, MEMS, various mixed signal die stacked together. What I don’t see happening is multiple logic die being stacked vertically. The challenges there are so much greater than putting memories and MEMS there, and the incentives are different. You can do it on much lower technology nodes. Stacking logic die together is a whole different ballgame. The first versions of that will probably be very homogeneous, like multiprocessors. Then all the TSVs are in exactly the same place, there’s no issue with dividing the logic because it’s all homogeneous. Heterogeneous logic stacked together is probably many years off.
Patel: The cost is more of a system configuration. The reason you stack different die is to make sure you reduce the cost on silicon, and then you integrate the lower node devices onto each other. Also there are power savings and form factor aspects. Cost has multiple facets. Only the system integrator can work that through and pass that down and define the boundaries for cost. If you look at the individual layers it may look cost-prohibitive. But when you look at the system model, you can figure out how to make this more efficient and cost-effective.

SMD: Somebody now has to take responsibility for the total cost as well as the risk if multiple known-good die or components don’t work together. Whose job is that?
Pateras: We’re moving toward the OSAT owning that process.
Ranjan: That remains to be seen. OSATs have certainly made aggressive investments. But when you look at TSMC, they control bumping for 28nm. TSMC decided to bring bumping in-house at 40nm. They do 80%-plus in-house. The reason they did that is one of their customers was having device failures. They could design the silicon but they could not integrate it with the bumping technology of the OSAT. They realized bumping is becoming a value-add and decided to bring it in-house. At 28nm, they’re going to do the majority of bumping in-house. We are learning now they are making assembly investments for silicon interposers. Why would they let the OSATs do TSVs? Why would they not do it internally. Their customers may force them to have multiple sources, but it remains to be seen who owns the integration. Outside of that, nobody has the ability to do memory plus logic integration except Samsung. The supply chain issues are very complex.
Patel: If you look at the semiconductor industry today, the majority of business is done through OSATs and collaborations, and ownership is distributed through various segments. By bringing in one entity you are no longer collaborating with the industry and the ownership becomes much more muddled. The best way to solve this is to collaborate, to understand where the handoffs are, and to make sure yield is understood at every point. Ownership should be distributed. That way the end customer can reduce the cost and the volume manufacturing flexibility will still be there. Last year we saw floods in Thailand and calamity in Japan. The industry needs a distributed ownership and responsibility rather than keeping it all in one place. That’s what we are trying to do.
Ranjan: You’re absolutely correct. But it’s a function of the lifecycle. Where does the lifecycle get distributed? Initially, companies may own more portions than in the past. But as the products get more mature, that will be distributed. Collaboration works very well in the R&D process now. But when you ship one wafer out that gets integrated with a memory chip and all of a sudden you have people pointing at each other over yield and asking for money back, collaboration doesn’t work well at that point.
Patel: Fifteen years ago we went through flip chip on laminate. IBM was doing flip chip on ceramic, but we moved to laminate and there were no easy answers. It’s the same for TSVs. The OSATs came up with bumping capabilities. Subsystem suppliers worked on the design capabilities. And they worked on that together. If it worked then, I don’t know why it wouldn’t work now.
Pateras: The other challenge is who’s going to take over test in 3D. You can’t package it if it’s untestable.
Patel: Typical products will require logic plus memory. How many products will be configured and put through the mainstream?
Ranjan: From our perspective, it doesn’t matter who does it—as long as the market grows.

SMD: Where does EDA come in?
Smith: One of the things that’s needed is for designers to be better educated about this technology. I first started working with 3D several years ago, and you can quickly get into it. There are a lot of papers and conferences. Time and time again, we go visit our customers—design teams, design managers, CAD teams, CAD managers, and even our own executives—and you get questions about what exactly is 3D-IC. There’s a lot of education required for designers to even start thinking about whether this is feasible for them. The business aspects are one thing that drives companies like Samsung and Xilinx and Altera to do what they do, but there are thousands of design companies that could benefit from silicon interposer technology today. It’s a matter of getting them up to speed, training them and giving them the tools. It doesn’t require any manufacturing education. The designers just need to understand what they need to analyze and test and build into their designs. Pateras: We finding that we’re becoming the teachers. It’s amazing how many customers are coming to us and asking, ‘How do we do 3D? What do we need to do? What is the design process? What are the steps you need to go through for test and verficiation?’ We’re doing our best to define solutions, given what we know. It will be an iterative process.
Patel: For stacking configuration, one of the things that’s important from a design point of view is how to deliver power from the board to the top die, and what type of changes you need to make in the design.
Smith: What do you need to do differently in your logic die, which is typically on the bottom, with TSVs or an interposer or electrically or routing? What comes to mind is that we become the guinea pigs in EDA for the foundry reference flows. We’re often asked way in advance to provide tools to the market. We have to provide the foundries’ first foot forward into the design community. There’s a lot of investment there, and it’s not always clear when you get the return.
Pateras: We’ve had our 3D stacks up for more than a year. We announced test a year and a half ago. TSMC has had its 3D reference flow for more than a year. But I don’t think anyone’s doing it yet. It’s the leading edge priming the pump.
Smith: It’s a necessary investment and form of research. Part of our pain is that we need to do it without seeing any immediate business. But it gets there eventually. That’s the key. And we do learn from it. The way it works, since the first reference flows came out about 10 years ago for a new process node, is that a set of new requirements came into play. This is branching out into other areas now like analog and mixed signal reference flows. FinFETs will come next, along with silicon interposers and TSVs. It’s an interesting concept, and from an interoperability point of view we all know the kind of language we need to use when talking to the design teams and the foundry. The flows are well understood.