Experts At The Table: The Sky Isn’t Falling

Part two of three: 3D testing and business challenges, thermal issues, modeling approaches.

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By Ann Steffora Mutschler
SemiMD sat down recently to discuss how the industry is making 3D ICs a reality today with Sylvan Kaiser, chief technology officer at Docea Power; Steve Smith, senior director for 3D-IC strategy at Synopsys; and Dr. Ahmed Jerraya, director of strategic design programs at CEA-LETI. For part one of this series, click here.

SemiMD: Because CEA-LETI has direct experience with this, what was the biggest challenge to creating the 3D design prototype?
Jerraya: Here we will talk about the design side—putting things together—because on the technology side you have some challenges. In putting things together the key problem was the estimation of what we will have inside on the physical side like the thermal aspects, for example. Here in many aspects we were progressing in a blind way, we didn’t know what will come out even if we made some simulation but still in fact the tools are in early phases of doing this. Also, testing was a little bit of a challenge.

SemiMD: What aspect of the testing was the biggest challenge?
Jerraya: Everything had to be invented because you need to imagine a new process for testing. There is lots of theory about it the last two or three years. Lots of people are talking about good theories that were helpful for what we did. But the problem is you need to make choices. It’s like if you are setting standards or something like that. It’s not very simple. You need to make decisions.
Smith: [What CEA-LETI did] is an example of what a semiconductor company is going to have to deal with when doing this for real. I don’t mean they didn’t do it for real—they did—but not in a volume-production, commercial environment. It’s obviously at a different scale when you are doing it in volume and you need to test to a high degree at least those components or parts that are most likely to fail in the system. There are question marks now as far as what are the elements of the 3D stack that are required to be tested because they are out of their failure mechanisms. Is it the TSVs, the microbumps and so on? One of the challenges that we’re also hearing is the mechanical aspects of testing the die, either on the wafer or after being microbumped. Are we going to have probe pads or probe pins small enough to be able to do that? Do we need to create new test access methods? There’s a lot of theory around that, but again, we still haven’t seen any real commercial products in the marketplace and so, while it might seem like a good idea to say, ‘EDA needs to do better,’ we always come after the commercialization of technologies. That’s always been the case and we’re not going to be first this time…I don’t think there’s anything unusual about that. I think the brave, maybe the foolhardy, go ahead regardless and they figure it out and eventually they make things work. There are a lot of smart people in the industry. In my opinion, if I was to answer the question…the biggest impediment is not a technical one, it’s again more of a business one. When does the economics make sense for a particular product? Or it may be a risk reduction. Who is going to take the first stab of putting a project on the table – putting up that challenge of flying to the moon with 3D IC?

SemiMD: On the thermal side of things, what technically has to be done right now to get people ready for 3D?
Kaiser: The thermal issues even for 2D or 2.5D are increasing because of shrinking geometries, so that is just a logical progression of the technology. People are more and more aware of these thermal issues even for 2D, but with 3D it’s certainly exploding. That’s interesting and everybody is worrying about that. I think one of the first missions I would say is to explain that there are actually several issues already linked to temperature. Thermal is not only one thing. You can talk about very localized thermal issues relative to mechanics in 3D relative to TSVs. You can talk about thermal gradient over the whole chip that will cause timing issues between the IPs communicating and you already can talk about thermal budget globally on the system. This budget may be imposed by the system manufacturer or the equipment manufacturer because you cannot have a handheld device at 100 degrees Celsius. So in terms of temperature and thermal issues, there are several aspects relative to thermal issues.
Smith: Certainly the phases are awareness and education because you don’t want to be surprised; and then comes modeling and analysis and having that available so that smart engineers can use techniques to redesign or circumnavigate the issues. The last phase is the automation. You can only automate something when you know what steps are the best. With 3D IC what we’ve got today is a basic toolkit that you can actually use today’s commercial IC design tools to add TSVs and routing, and things like that. But you still have to have the smarts of the system engineer to package it around it. That hasn’t changed and that’s not automated in any tool today. All you can do is analyze and verify. There’s no automation.
Kaiser: Yes, it’s like a pyramid: You have to have the models and to really understand which issue you would like to tackle and the appropriate model for that. Below you have the tool, and on the base you have the methodology, which provides the automation. And this pyramid has to be constructed for temperature analysis.

SemiMD: We need to do a lot of modeling. We need to model the TSVs, the package, what else do we need to model and how are we going to do it? What is the best way to approach this?
Jerraya: There are two dimensions you need to think about. First, it’s all different physics you are going to model. And second, you need to model these at different levels. Today, for PCBs, we have lots of tools working on the physical level for PCB, but for this kind of integration…the iteration is so long and so expensive that you need to make sure that what you are doing is right. This is why you need to analyze all the different physics—mechanical, electrical, thermal—and you need to do them at the higher level before you design the different chips that you are going to integrate together. And then, of course, you need to model at the physical level what we are doing in the PCB. The most important thing is modeling at the higher level before your final implementation.
Smith: As you’re going to decompose the system into multiple chips or components or even in a single IC, you’re going to need a budget across the entire chip. It’s typical in a complex design today or a system that you may have tens or hundreds of design engineers, each with his own budget or block of chips to deal with. Ultimately you can be more accurate in smaller parts of the design, which maybe is necessary to make sure you achieve the budget. Nobody wants to be the one that goes over and then has to steal from another neighbor. That’s a methodology that’s been evolving for decades and I think it’s another dimension that you have to take into account, but it’s still driven by the overall system architecture or the environment into which this 3D IC package is going.

SemiMD: When we talk about modeling at different levels, is this a single model or that we can pull different characteristics out of? How will that look technically?
Kaiser:  For thermal simulation, one of the new issues with 3D is that TSVs might have a big impact at the same time. They are very small devices and today it’s not really established when and with which format will be provided to the designers. That’s something that must be solved and tackled today. The best way to deal with that is to discuss it with the foundries with the companies enabling the technology to understand what will be in the flow, what they will be capable of providing and at which stage in the flow.
Jerraya: It’s like we are adding new devices in the design. For a design kit you will need to have the corresponding p-cells, the corresponding rules for constructing functional devices, and all of these need to be inserted in that design kit.
Smith: There are different models for different aspects and it’s truly fundamental, and maybe this is where EDA or at least the tools come into play. There are certain basic tools that can be used to do early analysis of new devices. For example, in the area of through-silicon vias, the TSVs have been well known for decades but never really embedded within a silicon process in real life. A lot of the early research was done with finite element analysis type of tools to model a single TSV and its surrounding silicon area. That’s one model, and it’s done to provide the building blocks in which to create a higher-level model in terms of electrical characteristics, thermal characteristics and so on, that can be put into a PDK or a design kit along with a set of design rules. But there’s not going to be one model that rules all. There is nothing unique about this other than the fact that it’s relatively new, but we are getting to the point where the real stuff is coming very soon.