Experts At The Table: Yield Issues

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss yield with Amiad Conley, technology marketing manager for yield and process control at Applied Materials; Cyrus Tabery, senior member of the GlobalFoundries technical staff for lithography development and DFM; Brady Benware, engineering manager for diagnosis and yield at Mentor Graphics, and Ankush Oberai, general manager of the Fab Analysis Business Unit at Magma Design Automation. What follows are excerpts of that conversation.

SMD: Does a shortened time-to-market deadline require more DFM or less?
Tabery: If it’s so short, then the ramp is just as important. The ramp is usually proportional to peak yield.
Benware: That’s why we’re addressing the cycle time for implementing DFM. It’s real-time verification while you’re drawing the polygons. But when we implemented that, the customers used the extra time to do more DFM. They didn’t change the tapeout time. As you improve DFM, you see people doing more within that window. The other challenge is that you have all these rules, but it’s hard to quantify which ones you should do. How much will your yield change if you follow a particular rule?
Tabery: It’s expensive to do it. So it comes back to the same cost question. There is uncertainty in DFM rules. The base rule is 20 and we’re debating for the DFM rule to be 26 or 28. We’re thinking about characterizing that slope of yield versus closure. But you’re talking about parts-per-billion failure rates, so you need to make billions and billions of these vias to check whether that adds 1% yield and it isn’t worth it or whether it adds 10% yield and it is worth it. Characterizing that roll-off curve is fundamental. But how do you bring those all together to have a useful model and to be able to synthesize that into a design rule. Uncertainty is expensive, but it’s also expensive if you can’t get your yield up faster. Both inspection and the EDA community can help us determine whether it should be 26 or 28 for that recommended rule.

SMD: From the equipment side, is there more influence from the design side or the foundries as we move to advanced nodes?
Conley: I’m not sure it changes. The restrictive design rules today involve the pitches in logic to make them more uniform. These are gridded design rules. This helps inspection because everything becomes uniform. The tools can find the defects more easily. The challenge we see is the complexity of recipe creation, which is why we are bringing design into the fabs. The foundries have a huge number of products and they do need to inspect every product because each product is from a different fabless company. They need to create a recipe for every product. They have numerous memory areas, and these can be identified ahead of time if we have the design built. This is what we’re doing with Magma.
Oberai: The users don’t want recipe creation as a manual process anymore. It’s too complex. They want some correlation to design geometries for incoming designs. They have to create hundreds and hundreds of recipes.

SMD: How does 3D stacking affect yield?
Conley: It’s a totally new game. You invest all the cost in working die, and you have two or more working die, and in the process of stacking you can encounter problems and lose everything.
Benware: The biggest challenge in 3D stacking is in test. How are you going to test these devices and make sure that two devices that were tested independently will work when you bring them together? And once you bring them together, how do you test each device individually. The challenge isn’t yield. It’s test to get to yield.
Tabery: We have packaging yield. We have models for that to know how it works. Putting two chips together is another process step and you have to understand the yield for that, but the yield targets would be very high because it’s using die that are already qualified and tested. The testability of that is interesting. How many TSVs do you need to test?
Oberai: We are seeing more and more of that. We are moving from die- or wafer-level navigation to board-level navigation. We put the whole board in a TM. Customers want to test the whole board. You test what the interconnectivity is. There are software capabilities to model this. It includes leakage and durability of connectors and what are the other effects of powering up the whole board or stacked die. But there isn’t anywhere near the level of tools for stacked die that we have on a single die.

SMD: There’s also a push to thin out the wafers in stacked die. How do you deal with that?
Tabery: It’s thinned out after the processing, so the impact on wafer processing is small. But there are additional mechanical and packaging challenges.
Oberai: It’s more the mechanical aspects.

SMD: Doesn’t that create more defects?
Tabery: It certainly could. You polish on the back side so that’s less risky, but if you induce a crack or there’s new stress that isn’t modeled, you need to understand that. The TSVs cause huge stress fields around the transistors. If the ones to the right of the TSV are slow but the ones just above the TSVs are fast, that’s no good.

SMD: 3D also blurs the lines across the supply chain. Who’s responsible for problems in complex chips and how do you deal with these problems?
Conley: The partnership between Applied Materials and Magma is part of this answer. There needs to be more partnerships between companies to solve critical issues. You need to take the advantages of each company and try to creation solution that is greater than the sum of both parts.
Oberai: In our partnership we are the ones creating the framework for the data depository and correlation and creating recipes and then sending it to the tool. The onus is on us to make sure the recipe generation has taken into account all the different elements. But we are heavily reliant on the tool providing all the parameters. Hopefully, when that happens there is alignment. We build a golden-case model to run sample recipes. If the recipe works we need to calibrate how long before we need to model again. The collaboration between companies is critical. The timekeeper is the customer or the fab. There are a lot of metrology tools and they are signaling these things. You never saw this kind of cooperation before. The onus is on all sides. There is enough harmony in this business to make this work. This is going to be an incremental process, though.
Benware: There’s a requirement for more interaction. We have to partner with our customers to be successful. While we see that test, manufacturing and design need to be linked, where we see the biggest challenge is in ownership of data. Somebody owns the data and someone else needs that data. Between the fabless company and the foundry, on the design side you have all this data and that needs to go to the fab somehow so they can do their process tuning and inspection based on the design. And it’s no longer just GDS. There are parametric and timing issues, so there’s more design data that has to go. At test you collect a whole bunch of failure data. Who owns that data? Someone had to take the wafer and scrap the wafer. Who owns that scrap wafer? Once you have the test data, you have to do yield analysis and that’s design information again. The fabless company owns the design information but it’s the fab that has the result. Where the data exists and how to transfer it between companies between exists today.

SMD: Isn’t that a mindset change?
Benware: Yes. There are IP concerns, too. Even if the data is encrypted, people don’t trust the encryption. And it’s multinational, so there are concerns with that. Even though vendors are providing these kinds of capabilities, one of the biggest challenges to the industry adopting it are overcoming IP and data-sharing hurdles that people are slow to solve.
Oberai: Even if there is a defect the foundry won’t give us the defect. You have to go down and look at it. They think, ‘What if it has something to do with a design customer?’ There’s not much you can do with a defect. But there are a lot of constraints on data.
Benware: A few years back we were seeing a lot of resistance to adopting diagnosis and volume at fabless customers because they couldn’t figure out who would pay for the tools and who would use the data. Over the past few years we’ve seen that perception of an IP issue completely evaporate when there is a yield problem. These companies are sending the foundry absolutely everything. They don’t want to put anything in place ahead of time, but when the problem comes it’s like grease. People have experienced that enough that they’re starting to overcome their issues. That’s a testament that yield is a big problem and the foundry and the fabless companies are in this together.
Oberai: It’s all about yield.