Extending UVM To Analog

As SoC complexity has grown, so too has the need to model the analog/mixed-signal content in a similar way as the digital content to make simulation easier. One way to do this is within the context of the Universal Verification Methodology (UVM). In fact, this can and is being done today with UVM as it stands, according to a number of industry sources.

However, there is also growing interest to extend UVM to better address the unique qualities of analog/mixed-signal content.

Adam Sherer, verification product management director at Cadence, noted that two years ago Cadence published a book on advanced UVM topics, which includes a significant segment on extending UVM for analog.

“We really believe in this. There are challenges though,” he admits. “Right now what we’re finding is that there is a relatively small segment of the analog community and it’s a segment that also has begun to build digital/mixed-signal models using the ‘wreal’ part of the Verilog-AMS standard or the ’SV-DC’ (SystemVerilog Discrete Modeling Committee) part of the IEEE 1800-2012 standard. Those are the engineers that tend to be looking for this first.”

Some outstanding issues include the ability for engineering teams to determine when to use a full detailed analog model and when to use a more abstracted model. “There are balances between the two. With the full detailed model, the simulation will run effectively as fast as that model, even if it’s a VHDL-AMS or Verilog-AMS. That is significantly slower than the digital RTL speed,” Sherer explained.

Interestingly, he noted, the piece that tends to bring in UVM and start this cascade of thought is using a digital/mixed-signal model. Traditionally, these were simple Verilog reals or VHDL real values, and the difficulty with them was that it was not possible to do any signal combination or superposition. The wreal, the SV-DC, add these resolution functions more accurate models can be built. “Once you get that model going, all of a sudden everything else comes into picture: What about analog assertions? What about analog coverage? What does the metric-driven verification process mean for analog?”

As a starting point, Cadence recommends users start with the modeling and make sure the simulation speed is good. Then, start exploring for their specific design needs, what does functional coverage mean for analog? What do assertions mean?

Also about two years ago, Synopsys started working with its user base to look for opportunities to better associate the UVM methodology with analog/mixed-signal designs, according to Steve Smith, senior director of marketing, mixed-signal verification at Synopsys. He pointed out, that “while it’s true to say that you can use UVM even in its current form in an analog/mixed-signal environment, you’re really driving it from a digital viewpoint. UVM as it stands today is purely digital from a testbench point of view. What that means is that if you have a system on chip whose interfaces to the rest of the world happen to be digital signals — you can drive them with logic ones and zeros — you could use UVM to drive that system on chip design even if it had some analog content within the chip itself.”

“Unfortunately,” he pointed out, “many mixed-signal designs actually have analog interfaces to the outside world. They are driving multi-controllers, and maybe they are driven by data that is coming from sensors that deliver analog voltages into the chip and they get converted within the chip for processing. In some cases you might want to create an environment for testing or verification, where you want to drive analog-type signals into the simulation. For example, you might want to wiggle a signal to make it look like a sine wave, or there might be other forms of waveforms that you might want to generate that are more analog type. The other thing is, within a mixed-signal environment, if you have analog content — which you will — inside the chip, you want to be able to monitor what is going on between the interface between the digital and the analog. [These] are often causes for design errors because designers may inadvertently misconnect some of the signals together so you want to have monitor points, otherwise called assertions or probe points. An assertion is something that will flag automatically during the simulation so what you want is those assertions to be able to recognize changes in analog signals as well as digital signals.”

This task involves the ability to set up assertions that monitor, other than logic zeros and ones, something that transitions across the voltage threshold or something more analog. “That of course requires not only an addition to the methodology which is based on SystemVerilog models and also the tools themselves – the simulators have to be able to react to that change in that signal,” Smith said.

To bring these issues and abilities more to the forefront and expose the concepts to more design teams around the world, Synopsys has extended UVM with a notion of analog/mixed-signal. “We’ve added to the UVM basic capabilities, and we’ve also added to the simulation tools that support the analog side to make them work even better in a mixed-signal environment,” he pointed out.

A loaded topic
Martin Vlach, chief technologist for analog/mixed-signal at Mentor Graphics, said these issues are tricky. Even the term ‘UVM’ itself is a loaded topic because at one level UVM is a very specific set of classes. “It has a technical meaning, but people generally don’t consider that. Generally when they talk about UVM they are actually thinking about the larger set of questions and issues that need to be considered for any type of verification, whether it is digital verification or analog verification.”

From his point of view, there are a number of important trends in regard to UVM.

First, composability. “You can actually write these tests and sequences and ship them along with your IP, and they can be re-used at the SoC integration level later on. This composability is a kind of basic feature of the whole methodology,” Vlach said. Second, is that UVM controls the inputs, observes the outputs, and observes fault conditions. “We would have the constrained random for the stimulus, self-checking testbenches that verify our coverage has been reached, and if it has, then it can stop the generation of the random stimulus. If it has not, it goes on and generates some more. People use this constrained random, and have been for probably 15 years at least, because the space to explore in digital systems is just so bad. Directed testing is not possible.”

Third, is reuse. “I call it the ‘simplicity’ of object-oriented approach, because any object-oriented approaches are going to pretty complicated. And you have all these computer scientists who have come into the digital verification space [of which he counts himself a small part of], and it is not for the faint of heart. UVM, the object-oriented part, is not for the analog engineer. The pure analog engineer is just not going to be interested in looking at it. The analog designer, those who are the really good ones, they know what they know, and what they know is so important that doing something else is not worth it for everybody.”

In terms of extending UVM to analog, Vlach is not sold. “For pure analog, I don’t think that anybody is going to be doing UVM because the kind of complexity that exists for pure analog design is not solved by UVM. There is a lot of complexity in analog design, so the expense of setting up the testbenches is really pretty huge. We do that already, by the way. People are actually doing it…for checking models in mixed-signal design. There, checking models, making sure that models in analog are good enough for verification, is a pretty unsolved issue. I have seen people who are beginning to do this…That is where UVM could be applied well.”

Evolving UVM
What needs to happen next in terms of evolving the way that the industry looks at analog/mixed-signal in the context of digital would include an interpretation or an approach for functional coverage and for assertions, Sherer said. “As those two begin to coalesce — and I know this from standards work and from Verilog-AMS around analog assertions in Accellera that there is some work that is going on in that space — as the industry begins to push those, you then have a model that you can begin to create stimulus for, do measurement around, do debug around. That’s what we would need to bring back to the UVM working group in order to make a proposal. My sense is that the work is still early. We may be approaching the critical mass in the industry in which to start a standards effort, but the pieces are still in motion.”

Given the timelines in the mixed-signal space this could be happening pretty quickly, he said. “It may be happening in the next couple of years as we drive down into the deeper process nodes with power, analog, digital all on the same die. We’re all competing for space and function and as those designs are attempting to tune themselves tighter and tighter, we really need to worry about that. There’s general functionality of analog and digital together, but if you add power into that picture, it adds a whole new dimension of complexity.”

There will also need to be some consistency of the IP environment, Sherer added. “You see all the pieces come together, you can imagine IP suppliers both digital and analog and maybe even a mixed signal supplier have to provide interfacing information, testbench information and even power format information. That has to integrate with others into an SoC. Each of those suppliers needs to figure out what they’re actually going to supply. They know it on the design side — that part is clear. I would expect at some point the big SoC integrators are going to come back, and that’s when you’ll start to see the standards community move fast because it would be increasingly difficult to integrate all those great IP blocks — they are great on their own and we have to bring them together.”