Chip floorplanning and macro placement using AI-based techniques such as machine learning (ML).
The chips contained in today’s consumer and commercial electronic products are staggering in size and complexity. The largest devices include central processing units (CPUs), graphics processing units (GPUs), and system-on-chip (SoC) devices that integrate many functions on a single die. Additionally, chips are expanding beyond their traditional borders with multi-die approaches such as 2.5DIC and 3DIC as a way to improve data transfer and mix technology nodes, which will propel applications like autonomous vehicles to improved efficiency and cost.
This white paper focuses chip floorplanning and the key step of macro placement, which is crucial for satisfying PPAC requirements: Similar to building a house or a skyscraper, a floorplan is a blueprint to build a chip that delivers the desired PPAC results. As in so many areas of technology, AI-based techniques such as machine learning (ML) can play a big role in taking floorplanning to the next level.
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