Methods for understanding how and why chips fail and how to improve yield.
ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed, mature yield is suboptimal, and product quality may suffer, thereby threatening a manufacturer’s profitability. Diagnosis-driven yield analysis is a methodology that leverages production test results, volume scan diagnosis, and statistical analysis to identify the cause of yield loss prior to failure analysis. This methodology can reduce the root cause cycle time by 75% to 90%. The methodology can be expanded with DFM-aware yield analysis to help separate design and process related yield limiters.
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