tag: yield analysis

Installing Yield Software Early In A Ramp Up
By Dieter Rathei - 10 Oct, 2023 - Comments: 0

In 1999, the White Oak Semiconductor Fab in Richmond, VA, was awarded the prestigious “Top Fab of the Year” (yes, that actually existed – proof attached!) by the leading semiconductor magazine of the time. Back then, I was a young engineer on the ramp up team and I recall that the reason we were chosen for the award was the incredibly short time in which we were able to ramp up production... » read more

Elevating Production Testing With Deep Data Analytics And ACS At The Edge And Cloud
By proteanTecs - 12 Jul, 2022 - Comments: 0

The level of system integration continues to increase at a rate of greater than 30% per year — fueled by the industry’s desire for increased capability, advanced process nodes, and "more than Moore" packaging techniques. Co-optimization of the hardware and software have also been required not only at the design stage, but at test and in the field. This white paper will present how to ele... » read more

Benefits Of Outsourcing Yield Management Software
By Marie Ryan - 10 Nov, 2020 - Comments: 0

Microchip is a longtime yieldHUB customer. We work with a number of divisions worldwide. We spoke to Kasia Metlička-Sawicka, an Engineering Release Supervisor, Senior Engineer II-Product in Microchip Ireland to find out why she likes using our system. What do you do? I’m an Engineering Release supervisor/Senior Product Engineer. I oversee the engineering release group of technicians... » read more

Faster Time To Root Cause With Diagnosis-Driven Yield Analysis
By Mentor, a Siemens Business - 16 Apr, 2015 - Comments: 0

ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed... » read more

Yield Ramp Challenges Increase
By Ann Mutschler - 11 Dec, 2014 - Comments: 0

As semiconductor manufacturing moves down to smaller process nodes, there’s no doubt that it is increasingly difficult to ramp both test and manufacturing yields. One reason for this is simply scale. Smaller nodes translate into more steps and greater complexity in the manufacturing process, with attendant process variations. “Smaller process nodes increase the amount of embedded mem... » read more

Root Cause Deconvolution
By Mentor, a Siemens Business - 19 Jun, 2014 - Comments: 0

Scan logic diagnosis turns failing test cycles into valuable data and is an established method for digital semiconductor defect localization. The advent of layout-aware scan diagnosis represented a dramatic advance in diagnosis technology because it reduces suspect area by up to 85% and identifies physical net segments rather than entire logic nets [1-3]. The defect classifications provided by ... » read more

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