Faster Time To Yield

Michael Jamiolkowski, president and CEO of Coventor, sat down with Semiconductor Engineering to talk about ways improve yield ramp and optimize designs. What follows are excerpts of that conversation.

SE: Why does it take so long to get a chip all the way through to manufacturing?

Jamiolkowski: There are three parts to that. There is a research side. You want to be able to explore new things and possibilities. There is the manufacturing side, which is going to take the normal amount of time for getting things ramped up. And then there is the ‘in-between’ phase—the technology development. It may take four years before a product reaches the market. That ‘in-between’ phase is where a lot of the hard work gets done, using a lot of short loop and learning cycles. You’re not just trying to create one device. You’re trying to create a billion devices. You are trying to use that process to address different types of structures, not just for one finFET or memory, but all the complexities and devices that might go into that process, as well. Then you have the BEOL and such. There is a lot of work that is going on during those four years. Traditionally, the way things worked was that it was these short loop cycles of one to three months. Then there were test chips, which might be out once per year. But it would take about three or four of those one-year cycles to be able to get them through, along with lots of the little cycles of learning. Our customers believe they can change this ‘in-between’ period to reduce the amount of time. We had a customer that did these virtual fabrications and cut nine months out of their development cycle.

SE: How?

Jamiolkowski: They used the virtual fabrication capability to come up with a better process integration flow. Otherwise they would have gone through multiple cycles of learning and iterations of those cycles.

SE: Do you find it helps in connecting the various pieces together?

Jamiolkowski: We talk about this as a funnel. Right now an engineer or development group has a shortage of wafers they can put into their experiments—maybe only 50 wafers a day to start, and they divide them into lots and splits. With virtual fabrication, you can run a bigger map of the process space. Instead of 40 or 50 real wafers, you can run 500 to 1,000 other wafers that might fit around it to help you identify the space around it—understand the windows, the variations, and maybe get some better ideas to use later on. It helps identify the best 40 wafers to put in, but also you never understand the full space unless you can run something like virtual wafers.

SE: Because it is virtual, how accurate is this?

Jamiolkowski: It is simulating what is going on, and it has proven very accurate and predictive. Our manufacturing and equipment customers, and Imec, will publish the accuracy and value of these results, so they’re already proving it.

SE: One of the big issues here is process variation. How does that work with what you’re doing?

Jamiolkowski: In some sense, that’s what our software does. When you put real wafers in, you can’t control those variations. You can try to isolate and experiment, but there are other variations going on. The equipment companies might have edge placement errors, CD issues, CD budget, and critical dimensions they have to worry about. If you can do lots of simulation and modeling with our software, you’ll have better ideas of where the weak points are and how to optimize the process.

SE: Some of the metrology and inspection tools that were used in the past don’t go far enough for the advanced nodes at 16/14nm and beyond. Can you extend those by identifying where the problems areas might be that they’d be looking for.

Jamiolkowski: We are working with metrology companies right now. They are looking for better ways to create one or two process recipes and taking information from multiple tools to put more holistic metrology together. Information can be added to our models and built onto it to see what it looks like downstream.

SE: So you are trying to determine what is going on at a deeper level and where you need to look for problems?

Jamiolkowski: Yes. We also have built-in metrology, so we understand all the sizes and shapes along the way at every process step. For all the other metrologies, you may not be able to go as deep or even find it. In some sense, we are providing a vision of what is out there.

SE: In terms of different process nodes, does it matter what node chipmakers are at?

Jamiolkowski: No, it’s any process. A customer originally started using us for MEMS, which are inherently 3D structures and devices that are moving and floating. Years ago, when Intel was one of our investors, they suggested that we adapt this for semiconductors processes. That’s when we started to add more semiconductor process steps. They never told us what they were doing with it, though. That’s where IBM came in. They helped us understand what to do. We are grateful for the collaboration we had with them. It doesn’t matter if it is 5nm or 7nm. We don’t know what is coming at 3nm, but we are trying to stay in front of where the market is. That’s why we work closely with Imec. And equipment companies want to share a bit because they would like to be ready, as well. We work with the equipment companies on the patterning and lithography.

SE: 2.5D and 3D process also can be modeled in terms of process?

Jamiolkowski: Yes, on 2.5D, 3D, and 3D-IC implementations. One of our customers is doing that right now. It takes process, layout, and builds something very accurately based on what it’s told.

SE: Some of this is moving down to the most advanced nodes, some is sitting back at the older nodes, and there’s more integration and more things going on inside these chips. How does that impact you?

Jamiolkowski: The most advanced nodes and memories are what is driving our business and attention. We do have customers in older nodes, but the higher value and the investment for their manufacturing isn’t as big of problem. We have customers that want to do studies to replace full cycles of learning. We did a 1M wafer study at Imec, to be published in December, for 5nm BEOL. We are getting calls from foundries now asking how it was done. This is the inflection point, the disruptive piece that I’m excited about. If companies get to market three to nine months faster, that’s a big deal. They may win that next major customer and get into the market more quickly. We are going to package our software to make it easier for companies to do the design of experiments. We’ll have a front-end virtual fab for analytics, and we’ll have back-end tools to help them manage the data on the analysis.

SE: So it’s time-to-market that you are seeing as the biggest problem, not the node or the technology?

Jamiolkowski: That’s the the biggest problem. There are also questions about which tools, which patterning, which process integration flows, and how slight the error in these solutions. Because of the equipment, the tolerances are so small. You have to make these things more accurate and the process has to be as good as possible. IBM and Coventor co-published a paper in 2013, where we proved they could use our software to predict a better, non-intuitive solution to a yield-limiting problem. It was something yielding two sigma, and it looked great at nominal. They used our software, cut a mask on it, and it yielded five sigma. That’s optimization. We are getting closer to that capability instead of throwing all those tens of millions of dollars away.

SE: If yield is ramping, then you basically achieved your goal, right?

Jamiolkowski: That’s right. Even for PDKs where people are calling for this earlier and earlier and getting a 0.1 PDK version, we think using our software we can get a higher level of PDK for the designers earlier. Maybe it’s not a 1.0. Maybe it’s a 0.5 or whatever the numbering may be, but you are skipping a couple of cycles of weak PDKs. We can come up with better design rules using it from the design enablement group to understand the process better and earlier.