Favorite Forecast Fallacies

It’s difficult to make predictions, especially about the future. – An Old Danish Proverb.

The GSA Silicon Summit was held on Thursday, April 10th at the Computer History Museum in Mountain View, CA. The opening panel session was entitled Advancements in Nanoscale Processing. The panelists were Rob Aitken (ARM), Adam Brand (Applied Materials), Peter Huang (TSMC), Nick Kepler (VLSI Research) and John Kibarian (PDF Solutions) and the session was moderated by Joe Sawicki (Mentor Graphics).

I believe it’s the challenge in making the future happen that makes these types of panels interesting. If it were easy and hence easily predictable, there’d be no need to attend. Everyone wants to know where process technology is heading and what promises those new technologies hold. The end of Moore’s Law has been predicted many times and the panelists were quick to mention many of these earlier predictions, so I thought it would be interesting to take a closer look at some of these and comments by the panelists.

John Kibarian mentioned that there’s been a plot used many times showing that the yield for newer, more advanced technology nodes is in a downward trend. I don’t know exactly which plot he was referring to, but he mentioned a circa 2004 timeframe, so I’m guessing it looked something like the plot in Figure 1. The data fits what was likely available around that period.

Figure 1. Yield vs. Technology Nodes [1]

Clearly this doesn’t paint a very optimistic picture, and this is back at 0.18µ. Five technology nodes later, how are we doing? John mentioned that some of the extrapolated predictions didn’t take into account the fact that layers weren’t being added as rapidly, and that advancements in processing technology actually improved defect densities per layer. 28nm is considered to be a good yielding technology, so the yield bus didn’t drive over the technology cliff after 180nm.

Rob Aitken mentioned that there was an often-used ITRS prediction, which said that by 2014 94% of the chip would be SRAM. That prediction is plotted in the chart in Figure 2.

Figure 2. Chip Logic and SRAM Area [2]

It’s also interesting to note the technology nodes predicted at each time period. Much to the semiconductor industry’s credit, it has tended to get new technology nodes out into production sooner than the ITRS timescale. Architects today are finding a lot of logic uses for all of those transistors that are available on a chip and part of that reason may be due to our next prediction.

In April of 2002, Pat Gelsinger, then CTO of Intel, was quoted as saying, “The numbers I would cite would be by 2010: 30GHz, 10billion transistors, and 1 tera-instruction per second.” Yes, very fast single-threaded machines may have had an increased need for more memory on-chip, although it’s interesting to note that the increased need for memory bandwidth may now become available by way of 3D through-silicon-via (TSV) technology. If we put ourselves back into the world of 2002, as shown in Figure 3, it’s easy to see why anyone would make that kind of prediction.

Figure 3. x86 Processor Clock Frequencies Over Time

From the late 1980s through 2002, or roughly 15 years, processor clock speeds were doubling nearly every 18 months. Extrapolate that out to 2010 and there’s no surprise that you’re looking at approximately 10GHz.

So what happened on the way to 30GHz? Back in 1999 Fred Pollack, then director of Intel’s Microprocessor Research Labs, gave a presentation at Micro 32 showing the now-famous power density plot with points plotted for a heat plate, nuclear reactor, rocket nozzle and the surface of the sun. I’ve taken that plot and annotated it in Figure 4 with the same set of processors.

Figure 4. x86 Processor Power Density

Power is basically what happened on the way to 30GHz, especially higher leakage that was very apparent at 65nm. It’s interesting to note that, compared to the 3.8GHz Intel Xeon processor released in November of 2004, over the past 10 years we haven’t really even doubled that frequency in standard commercial processors, x86 or otherwise.

Adam Brand mentioned seeing a presentation back in 2002 saying that EUV was the next big thing. People seem to believe that it eventually will come into play, but it keeps being pushed further and further into the future. Rob Aitken said that back in 1986 it was claimed that optical lithography was dead. I looked into this a bit and found that Rob was actually sandbagging a bit here. An interesting paper by Rebecca Henderson, Of life cycles real and imaginary: The unexpectedly long old age of optical lithography, discusses the persistence of optical lithography in the semiconductor industry well beyond its naysayers deadlines and mentions the call for the end of optical lithography back in 1977. Oh, and Rebecca published her paper back in 1995. Nearly 20 years after that paper, the semiconductor industry is still using optical lithography.

So what were some of the panelists’ predictions? Rob said that FinFETs look good to 10nm, may start running out of steam at 7nm, but still look to be workable there. At 5nm it’s possible that all-around gates/wires will come into play. Given that FinFET papers were published in the late 1990s [4] and wires in the mid 2000s [5], it’s certainly within the realm of possibility. Nick Kepler and John Kibarian both mentioned that economics will play a strong part as to whether the industry ever moves to 450mm wafers. Right now 80% of the wafer cost is in tools that process by area, so that doesn’t bode well for 450mm. But if new nodes were to appear at a fast pace, that could tilt things towards 450mm. In any event, it appears that an industry move to 450mm isn’t a foregone conclusion just yet.

I opened this article with a quote, so I’ll close it with another.

These results lend support to those that have argued that it is important to explore both the social context of a technology and the dynamics of the technology itself if one is to fully understand patterns of technological evolution. — Rebecca Henderson

[1] R. Sommer, DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield – Influence of Process Variations in Digital, Analog and Mixed-Signal Circuit Design, Figure attributed to Uwe Gäbler.

[2] ITRS 2000 Update.

[3] R. Henderson, , Of life cycles real and imaginary: The unexpectedly long old age of optical lithography, Research Policy 24 (1995) 631-643, Elsevier Science B.V.

[4] X. Huang, W-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H.Takeuchi, Y-K. Choi, K. Asano, V. Subramanian, T-J. King, J. Bokor, C. Hu, “Sub 50-nm FinFET: PMOS,” IEDM Technical Digest, Washington, DC, pp. 67-70, December 5-8, 1999.

[5] Fu-Liang Yang; Di-Hong Lee; Hou-Yu Chen; Chang-Yun Chang; Sheng-Da Liu; Cheng-Chuan Huang; Tang-Xuan Chung; Hung-Wei Chen; Chien-Chao Huang; Yi-Hsuan Liu; Chung-Cheng Wu; Chi-Chun Chen; Shih-Chang Chen; Ying-Tsung Chen; Ying-Ho Chen; Chih-Jian Chen; Bor-Wen Chan; Peng-Fu Hsu; Jyu-Horng Shieh; Han-Jan Tao; Yee-Chia Yeo; Yiming Li; Jam-Wem Lee; Pu Chen; Mong-Song Liang; Chenming Hu, “5nm-gate nanowire FinFET,” VLSI Technology, 2004. Digest ofTechnical Papers, pp. 196-197.