FinFET Learning

FinFETs are not simple to work with. They’re difficult to manufacture, tricky to design, and they run the risk of greatly increased dynamic power density—particularly at 14/16nm, where extra margin is hard to justify—which affects everything from electromigration to signal integrity.

Moreover, while finFETs have been on the drawing board for more than a decade, it’s taken four years to get to a process node where the largest foundries are willing to invest in new equipment to make them. Intel was the first to jump into finFETs, because it allowed the company to boost the clock frequency on its processors again by reducing leakage current, but even that hasn’t been simple. Reports of bad yield continue to plague the company.

Yield issues, to be fair, are nothing new at advanced nodes. They were problematic at 130nm, particularly with the addition of low-k dielectric insulation and the advent of copper interconnects. And they were troublesome at every node since. But the number of problems that need to be solved also rendered 20nm a non-player using 2D transistors, primarily due to leakage, which means the time between nodes is really four years rather than two. That throws off the pace that the semiconductor industry has used as its standard for progress since the mid-1960s.

FinFETs are another wrinkle in all of this—almost literally. By adding more gates to a transistor, it provides more granularity to control dynamic and static leakage, which finFETs can do quite effectively. They’ve been proven by Intel to work, and the processes around them are firmed up to the point where GlobalFoundries and TSMC have released version 1.0—enough to provide confidence for EDA toolmakers and their customers to move forward en masse. For early adopters, the tools are indeed ready.

There’s still a learning curve ahead, of course, and it’s a steep one because of the impact on every level of power. At 65nm, power was a side note. At 14/16nm, it determines how long transistors can be on, which transistors can be run at the same time, how fast they can be run and how they need to be connected to memories and I/Os. It affects which IP can be added and where. And it creates the need for much more sophisticated thermal mapping because the heat at the bottom of a finFET array is going to be higher than at the top. Put simply, leakage may be under control but the chip can still burn up.

Moreover, designers will need to be much more exacting than in the past. The extra margin that was inserted in previous designs as a buffer against worst-case scenarios doesn’t work anymore—or at least not on the scale that existed in the past. So while there’s been a lot of talk about first-time success, guard-banding was almost always part of the equation. It can’t be in the future, because the extra circuitry increases dynamic power and decreases performance.

Throw in lithography issues—EUV is now four process nodes late—along with the need for double patterning, more complex testing, new layout schemes and a bigger ESD threat, and getting new designs to market becomes even more daunting.

This is an industry that thrives on solving difficult and interesting problems, and there is enough collective enthusiasm and knowledge to solve any problem involving semiconductors. The question now—and one that’s unanswered—is at just how much controlling power of every type is going cost and how to get that cost down to something consumers will pay. Power is driving up the amount of engineering that needs to be done on every front, and it’s only going to be more pronounced as quantum effects begin forcing new materials into the equation.

We have much to learn. With FinFETs, it’s like hitting the reset button on education. It’s time to start all over again.