What improvements are needed for existing CAD and simulation tools to deal with advanced packaging.
As devices continue to become smaller and more portable Moore’s Law continues to increase the number of transistors that fit within a chip albeit many predict an end to this in the near future. However new interconnect technologies that use Through-Silicon-Vias (TSVs) can place ICs next to each other using 2.5D Interposers or stack chips in 3D resulting in even greater system scaling. This corresponds to non-digital functionalities that traditionally reside on printed circuit boards (PCBs) being migrated into a package or chip and has enabled the design community to begin “More than Moore” where Moore refers to “Moore’s Law.”
This change where chips are being interconnected using 2.5D interposers or 3D stacking presents new challenges because it becomes increasingly difficult to operate within a devices thermal envelope. This makes accounting for thermal early in a design extremely important to the success of any product. Recent rumors indicate that the Galaxy S7 will include heat pipes to successfully remove heat improving the devices performance highlighting how important innovative thermal design is becoming. Additionally the impact from just reducing silicon node size has placed great thermal burdens within traditional package sizes due to reduced trace-trace spacing and widths while maintaining the same amperage requirements. As the electronics industry continues evolving it requires improvements to existing CAD and simulation tools in support of these challenges.
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