Full AMS Design Flow For The IoT

By Nicolas Williams and Jeff Miller

The pressure for a new generation of (analog/mixed-signal) AMS design capabilities has been accelerated by the sudden demand for Internet of Things (IoT). These inexpensive devices are used in an expanding array of scenarios on the edge of the network — thus the demand for an AMS design environment that is affordable and easy to use, but powerful enough to create the widely diverse range of products needed for deployment of IoT.

Analog designers for IoT sensor devices require a set of design capabilities that support the creation of a mostly analog circuitry along with some digital—the so-called ‘Big A/little D’ designs. A new generation of affordable, easy-to-use AMS design tools is emerging that directly address these challenges, providing a complete flow tailored for the big-A/little-D AMS market for every stage of the design process. Analog/mixed-signal designers adopting these tools greatly benefit from the increased automation, improved accuracy, lower NRE costs and reduced time to market at every step in the design process.

Front End Design: When creating an analog/mixed-signal design, it is crucial to have access to multiple views per cell to handle schematics and RTL. Tanner S-Edit, an easy-to-use schematic capture tool, supports drawn schematic views, as well as SPICE, Verilog, Verilog-A and Verilog-AMS views. This allows designers to easily swap in abstract or detailed models on a cell-by-cell basis. Designers can quickly explore mixed-signal architectures using the abstract Verilog-AMS models before doing detailed design of the individual blocks. Integrated SPICE and RTL capabilities, such as those available in Tanner T-Spice AMS, allow for easy simulation with the full range of foundry models plus RTL digital co-simulation, providing precise characterization of complex circuit behavior for various transistor and behavioral models.

Physical Layout and Verification: The challenge here is to maximize efficiency when creating an IoT device’s physical layout. This requires a hierarchical physical layout editor, combining fast rendering and built-in productivity tools to support parameterized cells. That allows designers to create automatic custom layout generators or to easily setup layout generators for most common devices such as MOSFETs, resistors or capacitors. Interactive design rule checking (DRC) will display violations in real time, helping designers quickly create compact, error-free layouts. Layout teams will want to maximize productivity with a full schematic-driven layout flow, where the schematic and layout stay in sync, including cross-probing and automatic ECO flagging.

For the digital portion of the IoT big-A/little-D, the design flow should include a complete logic synthesis tool to synthesize and optimize for area, power, timing and design-for-testability (DFT). It also should include a highly integrated place and route tool that gives full control over every step of the process. The high-speed, big-capacity, static timing analyzer (STA) for nanometer timing analysis and sign-off. A designer can then perform true co-simulation of the analog and digital blocks with parasitics, including signal transitions across analog/digital boundaries.

Full-chip assembly: Designers need to instance top-level blocks and place them using real-time flylines to minimize routing congestion, allowing them to quickly check for connectivity issues. An effective approach is to run this in the cell’s context and highlight errors without having to run a full LVS. An automatic routing engine speeds layout of top-level chip assembly routing. This makes it possible for designers to focus on routes that require hand craftsmanship—either for performance or addressing analog-sensitive nets or parts of nets. For all remaining circuitry, the router automatically routes the noncritical nets, based on user specific widths, with support for multiple vias.

Getting to Market Faster
Designers working on IoT analog/mixed-signal projects face a slew of challenges due to increasing functionality and complexity. In addition, the cost-sensitive IoT market demands aggressive time to market and reduced re-spins. Mentor Graphics Tanner AMS IC design flow offers designers a comprehensive tool suite that is easy to use with a price-performance unmatched in the industry.

To learn more about Mentor Graphics Tanner AMS IC Design tools, click here.

— Nicolas Williams is a product marketing manager at Mentor Graphics; Jeff Miller is a technical marketing engineer at the company.