Getting To Tape-Out Quicker With Analog Layout Generators

All design engineers know it well: there is hardly any time left until tape-out, but the amount of work that remains is not decreasing as fast as the deadline is approaching. The intricate schematic must still be implemented as a layout, and many recurring tasks slow down the progress. The real crux often lies in specific parts of the circuit – parts that often have lower performance demands but are necessary and take up a great deal of time in the design stage. Can automation help to save time here?

Digital IC design shows how it’s done: The synthesis ranges from the hardware description to the layout. This comprehensive automation is the key to the enormous size and complexity of today’s integrated digital microchips. But great progress has also been made in analog circuits in the past.

Scripts and procedures can be used for analog circuits to handle repetitive tasks. For example, these can relate to estimating the circuit performance, checking for simple but easily overlooked errors or the automated, common centroid arrangement of devices. Designers can control such scripts via parameters and in some cases even GUIs, making them transparent tools that can significantly increase productivity. Approaches for layout synthesis also exist especially in the academic environment and increasingly also in commercial practice. Layout synthesis can be very powerful when the right constraints have been defined. Defining these constraints has long been possible in design tools, but this option is still rarely used consistently. However, an optimal synthesis with good results is impossible without this information. As a result, the obstacles to taking advantage of the synthesis are often too high or the synthesized results do not sufficiently meet expectations.

The simpler way is therefore the use of scripts and procedures. Or to put it more precisely, the use of generators. Interesting developments have taken place in this area in recent years. There are generators for schematics, for test benches, for simulation control and for layouts as well as generators that produce such design data as a “package.” Some approaches use pCells and others generate hierarchical cells and views, as are typical in manual design. Some utilize simple scripting languages for this, while others for example use the powerful Python language or other programming languages.

In general, generators take parameters entered by the designer as input and output corresponding design data. Generators are therefore tools that offer designers particularly effective support for recurring tasks. These could be layouts for basic analog components (current mirrors, difference pairs, etc.), but there are also generators for place-and-route, which place and interconnect many library cells or devices in complicated patterns. Some generators are independent of the semiconductor technology used. In this way, they also open up a path to faster migration between semiconductor technologies and foundries at the schematic and/or layout level. Additional tools that translate existing circuits into generator source code further simplify the process of migration and also enable the creation of a generic library of circuits for reuse in other projects.

Generators are therefore a tool that can significantly increase efficiency in various design phases. At the same time, the designer always retains full control over the process and obtains predictably fast results, which can be inserted as an automated component into the overall circuit. Designers can then concentrate more on the part of the circuit for which creative solutions are required, delegating repetitive and time-consuming tasks to the computer. In other words, generators represent a valuable tool for achieving good tape-outs on-time and without extra work.

For more, see: https://www.eas.iis.fraunhofer.de/en/research_topics/ic-design/intelligent-ip.html