Future generations of chips may require a sacrifice in functionality to stay within power and performance budgets.
By Ed Sperling
What do you do when you can’t fit any more functionality on a chip without blowing your power budget?
That question is being debated inside IBM right now, and one of the more radical concepts is to actually have systems do fewer things.
“That trend will happen,” said Brad McCredie, chief architect of the Power6 chip and an IBM Fellow. “I think devices will become more specific. But there is great debate about this right now.”
McCredie said that if devices can do 80% of what’s now done on a desktop or by an existing device more efficiently than a device that does everything, then it can be a big winner in the market. “If it does 10%, no one will ever write a line of code.”
That may be the only way to actually stay on the Moore’s Law road map of delivering twice as many transistors on a piece of silicon coupled with the unwritten corollary to Moore’s Law, which is that performance will double as well. While companies such as Intel and IBM don’t trumpet their performance gains anymore, most customers still see performance as one of the main reasons to buy new equipment.
Exactly what process node this occurs at is unknown. With the number of challenges increasing at each node—engineers now must solve multiple problems instead of just one—solutions are coming at a systems level instead of a chip level. That means rethinking a device from the top down as well as the bottom up.
“At 22nm or 20nm, there will be a discontinuity,” McCredie said. “This will happen at both the transistor and the device level. The industry has been fueled by density. We integrate multiple chips into a single chip and multiple computers into a single computer. But at 20nm, you can’t do that anymore. You need everything from stacked dies to 3D transistors.”
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