The Growing Verification Challenge

Complexity in designs, more features and smaller geometries are making it much harder to verify that a chip will work as planned.


System-Level Design talks with Charles Janac of Arteris, Frank Schirrmeister of Cadence, Venkat Iyer of Uniquify and Adnan Hamid of Breker Verification Systems about the growing difficulty of verifying complex SoCs and what lies ahead.

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