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HBM Roadmap: Next-Gen High-Bandwidth Memory Architectures (KAIST’s TERALAB)

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A new technical paper titled “HBM Roadmap Ver 1.7 Workshop” was published by researchers at KAIST’s TERALAB. The 371-page paper provides an overview of next-generation HBM architectures based on current technology trends, as well as many technology insights.

Find the technical paper here or here.  Published June 2025.

Advising Professor : Prof. Joungho Kim.

Fig. 1: Thermal Management & Cooling Methods for Next-Generation HBM. Source: KAIST Teralab, under supervision of professor Joungho Kim.



3 comments

sam says:

thanks a lot, you are lighting the road;

Amba Prasad says:

Best Documents showing Logical Teardown of HBM
Physical Architecture, an apt associate for JEDEC documents on HBM.

B.S. DeepakSubramanyan says:

Informative, thank you. I’ve worked towards Photonics and hopefully fits in HBM.

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