Who needs to be involved for a high-level synthesis hardware design flow to be successful?
Hardware design using HLS is no different than the typical ASIC/FPGA design flow with the exception that C++/SystemC is being used along with HLS to create the RTL instead of hand coding it. The advantage of using HLS is that it speeds up RTL creation time and reduces verification time by producing bug free RTL quickly from a fully verified C++/SystemC source. The misconception that still exists today is that anyone can design using HLS to create optimal hardware. The reality is that you still need to involve all of the people in a typical hardware design flow including the algorithm engineers, the hardware/system architects, and the RTL designers if the expectation is to achieve results as good or better than hand-coded RTL.
Hardware design is hard
Not anyone can do hardware design using HLS for production ASIC/FPGA that is efficient for power, performance, and area(PPA). If this was true there would be no need for hardware/system architects or RTL designers. In fact, hardware design requires an in-depth understanding of memory architecture, concurrent processes, and optimization of algorithms running in software to create efficient implementations running in hardware.
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