High-Speed Test IO: Addressing High-Performance Data Transmission And Testing Needs For HPC & AI

By Lakshmi Jain and Wei-Yu Ma

The AI and HPC industries are rapidly shifting toward chiplet-based designs to achieve unprecedented levels of performance, as traditional monolithic system-on-chip (SoC) architectures face scaling limitations. This transition is fueled by the rise of heterogeneous integration, which is driving innovation across the semiconductor sector. However, this advancement also introduces greater complexity in chip design, necessitating more advanced testing methodologies and enhanced testing equipment to ensure signal integrity, accuracy, and optimal performance.

As semiconductor complexity grows, structural testing becomes increasingly challenging, necessitating high-bandwidth test data interfaces for at-speed testing. This ensures truly known-good devices (KGDs), high test coverage, and low DPPM rates within a reasonable timeframe. Achieving maximum test coverage for individual chiplets is critical before integrating them into complex 2.5D or 3D packages, as it helps prevent yield fallout when combined with other chiplets in a complete package.

The number of test patterns required for these complex devices has grown significantly, while the availability of general-purpose IO (GPIO) pins for testing remains limited. The speed of GPIOs constrains test data throughput, making it challenging to achieve efficient and comprehensive coverage for modern designs. Although conventional high-speed I/O protocols like PCIe and USB meet bandwidth demands, they come with the drawback of requiring costly hardware setups.

Increasing testing costs with complex heterogeneous chips

In HPC and AI computing chips, as functionality becomes increasingly complex, the number of validation steps also grows significantly. However, in scenarios where the number of IO pins is limited, the bottleneck often lies in validation time, which extends the product development cycle and significantly increases the test costs.

The limited availability of high-bandwidth test access ports, particularly in multi-die designs, underscores the need for an IO solution capable of operating at significantly higher speeds than GPIO. This solution should eliminate the need for additional hardware components or complex protocol support during initialization and calibration, all while maintaining signal integrity to align with the latest manufacturing processes.

Synopsys High-Speed Test IOs are optimally designed to address the demanding requirements of high-speed testing. This versatile solution allows a single I/O to be multiplexed for various functions: serving as ‘test ports’ during manufacturing, enabling ‘high-speed clock observation’ during debugging, and configuring as ‘GPIO’ during production. This flexibility makes Synopsys High-Speed Test IOs uniquely positioned in the industry to support comprehensive testing needs.

Benefits of high-speed test IO for simplified & reliable testing

Synopsys High-Speed Test IO IP achieves higher data rates than other test IO, matching the advancement in testing equipment and supporting high-speed reliability testing with no protocol demands. The key advantage with this type of IO is the simplified testing process which excludes initialization, calibration, or training sequence. The maximum speed for the IO has been carefully designed to ensure stability with no signal integrity concerns.

Additionally, this solution delivers power efficiency, a critical factor for HPC applications, by conserving energy in GPIO mode and during non-test scenarios. The single-ended I/O design offers an area-efficient, cost-effective solution. Its implementation is highly flexible and scalable, with no restrictions on the number or placement of I/Os. They can be positioned on any side of the chip—left, right, or around the perimeter—allowing them to be placed closer to the circuits under test. This strategic placement enhances verification efficiency and simplifies testing, providing greater convenience (figure 1).

Fig. 1: Synopsys High-Speed Test GPIO (HSGPIO) for test and implementation.

Enhancing IO performance & optimizing power with multiple modes

In moving towards chiplet design, many of the regular high-speed interfaces are no longer available on some of the individual chiplets. The die-to-die interfaces like HBM and UCIe handle the communication between the chiplets and occupy most of the ports available for connection, which limits the number of interfaces suitable for external test access. With package pins being a valuable resource, Synopsys High-Speed Test IO enables the reuse of the same high-speed test pins as low-power GPIOs during field operation.

This solution is highly versatile and supports various test scenarios, including BIST and Scan Test, to ensure maximum test coverage. Additionally, this design requires only a single-ended PAD for signal transmission and testing, simplifying board layout and effectively reducing the number of PADs needed, which improves overall utilization. This architecture not only ensures efficient testing capabilities but also enhances testability and maintainability during the SoC validation phase.

• Testing: During manufacturing, the High-Speed Test IO functions as a test port, enabling data transfer rates of up to 3Gbps between Automatic Test Equipment (ATE) and the SoC. It supports both bare die (wafer-level) and package-level testing.
• Observation: The IO can be multiplexed as a high-speed clock observation port on the RVP board, to observe the CLK
• Power efficient mode: In production, the same port is configured as a GPIO, operating at frequencies up to 200MHz, supporting low power mode

Summary

As SoC complexity continues to grow, effective testing becomes critical to ensuring functionality and achieving high yield. Synopsys High-Speed Test IO offers an innovative solution for efficient, high-speed testing of complex semiconductors. It maximizes the use of limited package pins, supporting both high-speed testing and low-power GPIO functionality in production mode. This unique solution accelerates testing by up to 6X, delivers high throughput on advanced ATE testers, and eliminates the need for complex interface protocols—all while meeting stringent high-speed requirements. Synopsys’ IO team remains dedicated to supporting High-Speed Test IO IP on advanced TSMC nodes. For more information, visit Synopsys Foundation IP.

Wei-Yu Ma is a technical product principal manager for Foundation IP at Synopsys.