A way to improve yield not just by eliminating defects, but also by resolving parametric and systematic problems.
As new products and processes are being introduced into IC manufacturing at an accelerated rate, yield learning and ramping are becoming more challenging due to the increased interaction between the design and process. Compared to random defect caused yield losses, systematic yield loss mechanisms are becoming more important, thus initial yield ramping process becomes more challenging. A “holistic” yield improvement methodology has been proposed and implemented to significantly reduce the yield ramp time and maximize the profit for the semiconductor manufacturer. This new approach to yield improvement bridges the gap between design and manufacturing by integrating process recipe and design information with in-line manufacturing data to gain an enhanced understanding and subsequent determination of the process and design architecture issues that affect yield and performance. With this methodology yield is improved not just by eliminating defects, but also by resolving parametric and systematic problems. The result is higher yield and performance in a fraction of time required by traditional “defect based” methods.
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