HotChips: Power8

It’s another year, another HotChips Conference and another update on IBM’s POWER processor. IBM continues to impress with its big iron processor, and this year it’s the new POWER8.

IBM announced more details of its new POWER8 processor at HotChips and IBM now joins Intel at 22nm, but with the twist that IBM’s process is based on SOI technology. The POWER8 quadruples the thread count of its predecessors, the POWER 7 and POWER7+, by going to 12 SMT8 cores per die. Figure 1 shows a comparison of the new POWER 8 to previous POWER designs back to the POWER5. IBM is claiming an impressive 1.8x gain in single-threaded performance and Figure 2 shows a better than 2x gain over POWER7+ in socket performance. The socket power consumption should remain about on par with the previous POWER7/7+ processors with the new POWER8 staying within the same power form factor.

Figure 1. POWER8 vs. Previous Generation POWER Processors (Source: IBM)

One of the ways that IBM is able to keep these new parts in the same socket power envelope is by using an on-chip microcontroller for power management. On-chip power management controls the voltages, where each core has its own integrated voltage regulator module. The presenter, Jeff Stuecheli, declined to go into details about the integrated regulators, but he did say that the inductors are also on-chip. This would appear to be a step forward from Intel’s fully integrated voltage regulators (FIVR) used on its Haswell processor, which still incorporates off-chip inductors. A big advantage of on-chip regulators is better controllability that allows the power management to be much more aggressive in terms of changing voltages. With on-chip regulators the voltages can be changed to their new set points much quicker than in comparison to their off-chip counterparts, thus leading to higher overall system efficiency.

Figure 2. POWER8 Socket Performance vs. POWER7+ (Source: IBM)

Figure 2. POWER8 Socket Performance vs. POWER7+ (Source: IBM)

Another way that these parts are more energy-efficient is through their use of very large caches to reduce how far data has to repeatedly travel. On-chip there is 512KB per core of L2 cache for a total of 6MB of L2, and then there is another whopping 96MB of L3 cache on chip. IBM then follows this up with its Centaur memory buffers, which contain 16 MB each of eDRAM for up to a total of 8 high-speed channels or another 128 MB of off-chip cache. This channel buffer caching can keep the DRAM from being accessed as frequently, thus saving even more energy.

This new POWER8 processor should help IBM remain competitive in the Exascale race. And perhaps, partly in recognition of the recent advances of hybrid systems up the Top 500 supercomputing list, IBM also announced the OpenPOWER Consortium last month to collaborate with other partner companies around the new POWER architecture. This will allow IBM to further leverage its new POWER8 processor into high performance computing markets.