How HLS can be used to improve the design, verification, and reuse of intellectual property.
Engineering teams are under more pressure than ever before—systems on chip (SoCs) are growing more complex and design schedules are increasingly tighter. With its productivity advantages, high-level synthesis (HLS) has long been touted as part of the solution, but its sweet spot has traditionally been limited to datapath-centric blocks. Moreover, design productivity is only one part of the equation. Verification is often an even bigger hurdle.
This paper discusses how HLS can be used to improve the design, verification, and reuse of intellectual property (IP) and an HLS tool.
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