How to Make Sure IP will Float in the Rough SoC Sea

The impact of coupling on designs and what to watch out for.


Today a typical SoC includes hundreds of instances of IP modules both digital and analog. These IPs are typically verified individually by the vendors. The burden of guaranteeing functionality when placed in the midst of a monster SoC is typically left to the SoC owner.

With increasing frequencies, tighter margins, denser integrated circuits, new devices and materials, the task of verifying SoC functionality can become daunting. Making matters worse, there is no standard methodology for chip-level verification in terms of coupling and noise from other modules. Coupling between different modules occurs through global distribution networks such as the power and clock distribution networks, the substrate, and far-reaching magnetic effects.

Magnetic coupling cannot be shielded because the relative permeability of interconnect and silicon is 1, similar to free space. They are practically non-existent in terms of magnetic shielding. Hence, magnetic coupling is far-reaching and easily can cause huge noise between different modules in certain switching conditions. Capacitive coupling on the other hand easily can be shielded by interconnect, and its effects are locally contained, so capacitive coupling is rarely an issue between IP blocks.

There are two extremes for how to deal with inductive effects. One is to perform full electromagnetic analysis, including inductive effects. However, full-chip electromagnetic verification is extremely complex and most EM tools cannot handle SoC chip complexity. The key culprit is the dense matrices associated with inductive coupling and the follow-on difficulty of simulations.

Note that the number of inductive coupling elements scale as the square of the number of extraction nodes. In comparison, resistor and capacitance matrices scale with the number of nodes. For a typical large coupled interconnect, the inductance matrix has 4 to 5 orders of magnitude more elements than anything else in the model (representing >99.99% of the circuit). At the other extreme, EM simulations are totally skipped and some practices are applied, such as leaving white spaces, adding margins, increasing power, differential switching, etc. This other extreme can result in unexpected and very expensive chip failures, or overdesign of the chip to kill any potential magnetic effects.

A middle ground between those two extremes is obviously desired to quickly identify the areas of high risk and then to analyze those areas of high risk to guarantee the functionality of IP modules when placed amidst other aggressive and/or sensitive blocks in an SoC environment.

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