A look at how to improve simulation consistency and to speed up lithography operations.
As the technology advances, OPC run time turns to be a big concern, and a great deal of our effort is directed toward speeding up the litho operations. In addition, the OPC simulation consistency sometimes deteriorates, which is a critical issue—especially for anchor features. On the other hand, full-chip designs usually comprise large arrays of basic cells, used by OPC engineers to tune OPC recipes, which is evident for instance for memory design and processor chips. The model-based OPC technique is not necessary for such designs, provided that the equivalent mask shapes for one cell of these arrays are already known.
In this work, we introduce a combined approach using model- and pattern-based OPC. Pattern matching is used to extract regions from full chips that match the basic designs stored in pre-created libraries. When matching occurs, the OPC solution stored in these libraries is used and populated across matched areas. Special treatment for large array boundaries is applied due to proximity effects. Model-based OPC is used for the rest of the chip. This approach has two main advantages. First, simulation consistency is greatly improved because the OPC solution for standard cells is known. And second, pattern matching is a DRC-based tool, and thus it is very fast compared to litho operations and hence TAT is further enhanced.
To download this white paper, click here.
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